Hi ShawnLogan and thanks for a detailed reply. I think I understood your ADC but I am not it corresponds to my question so I'll try to explain it more. My question is more discussion based. For a scenario in which you have a top-level chip to test and it has both analog and digital inputs, various, and let's say all in all you have to create 40 input signals and many are buses with bits you need to change from test to test. And you will be using ADE to create your testbench schematic. (and don't limit yourself to transient simulation only, you use these for dc simulations too) What would be your approach to creating the 40 signals? (in ADE) Through my experience there were times I would create those 40 vdc (or some vbit, vpulse) generators by hand, then go into labeling them... My other approach was to create a verilogams module with simple output structure with what I needed and then instantiate that cellview with its symbol, etc. .... but this was not favorable with other team members for example. Many preferred to see the generators for different reasons. Thinking about ways to make the process of creating this kind of testbench quicker I was hoping (for cases where you need to input bus/vector signals) to instantiate an array of vdc generators (the left side of my picture) like V5 and hoped that if I enter a design variable for DC voltage value like "vh " that it would create 4 different design variables in ADE. It didn't. I don't know if that is even possible or not. If it's possible maybe I'm not doing it right then...?
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