As I've said before, having power nets in the verilog won't help you since the symbols don't have power and ground nets. Similarly the verilog descriptions of the standard cells don't have power and ground nets. It's irrelevant what you specify as the global nets in the Verilog In form because those nets wouldn't be in the Verilog netlist (unless you've used the inherited connections trick I mentioned before, or you've got explicit pins everywhere, which probably doesn't make sense as part of a flow). I suspect all you need to do is ensure that the top level pins (on your P&R block) are called VDD! and VSS! or you have made those equivalent to VDD and VSS respectively (I expect Calibre LVS allows you to do this). I doubt it's essential for the pins to match on the netlist and layout at each and every level of hierarchy, or there's probably a way of mapping them somehow in Calibre. However, not a tool I have really used (as I work for Cadence not Mentor). Andrew.
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