Forum Post: Cadence Virtuoso: Import a large verilog netlist to cadence...
Hello all, I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors: Error: Net "v_CALCULATION_CNTR "...
View ArticleForum Post: RE: Assura problems with feedthrough caps
Hi Andrew, Yes, i guess it would be difficult but thanks anyway. I progress a little bit. Just in case it can be useful to somebody: I am having around 10000 ambiguities but if I increase the threshold...
View ArticleForum Post: RE: Donut Pad to Ground Connection
In the Symbol Editor, Edit>Properties, Pins On in Find, pick the Pin with a left-click, locate the Dyn_Thermal_Conn_Type entry in Edit Property and select it, use Assign, and set None for the Type...
View ArticleForum Post: Arguments in geOpen()
Hi, its showing an error for geOpen() with some arguments as missing, even after i specifed the every argument. geOpen(w_Window, library, cell, "schematic" "schematic" "r"), where i specified my window...
View ArticleForum Post: RE: layout dynamic selection accessibility?
In IC617 and ICADV122/123 the out-of-context (i.e. unselectable) items are now shown black (rather than grey) like the rest, but are shown italicised to make it easier to read. The answer to your...
View ArticleForum Post: RE: lxCheck but with useful return?
Dan, Try this: procedure(CCFlxCheck(cv) let(((port outstring())) ; might not want to capture the warnings - if not, miss out the (woport port) bit let(((woport port) (poport port)) lxCheck(cv) ) prog1(...
View ArticleForum Post: RE: Cadence Virtuoso: Import a large verilog netlist to cadence...
Thanks Andrew for your reply. I'll try a more recent IC version, but one more simple question.. in the design verilog netlist every std cell has "VDD"&"VSS" as power ports, while in the std cell...
View ArticleForum Post: RE: Cadence Virtuoso: Import a large verilog netlist to cadence...
As I've said before, having power nets in the verilog won't help you since the symbols don't have power and ground nets. Similarly the verilog descriptions of the standard cells don't have power and...
View ArticleForum Post: Storing config of a cell in a file/cellview
Hi, Is it somehow possible to store design variables of a cell in a config-like cellview or file? Here is what I mean: Suppose I design a simple opamp for I which create a triangle symbol view and use...
View ArticleForum Post: multi-technology simulation netlisting through command line.
Hi, All, I am doing top level mixed-signal multi-technology simulation (MTS). To generate a mutli-technology analog netlist, I need to start ADE XL GUI, config it into MTS mode, and generate netlist...
View ArticleForum Post: BER test setup in cadence
hi my question is regarding BER testing. I want to check the BER for OOK modulator/demodulator. I tried to find (in forum discussions) the setup/instances that may help to make setup for BER testing....
View ArticleForum Post: Trying to generate abstract using absAbstract() command
Hi All, I executed below steps in CIW. I am using Virtuoso 6.1.6 version. My main aim is to generate lef from layout without any GUI windows. absSkillMode() absSetLibrary("venu") absSelCell("INV")...
View ArticleForum Post: when is .cdsinit.local loaded?
I have a questions on .cdsinit.local file I did some customization (bindkeys etc.) in .cdsinit.local file and I put the file in my cadence working directory. When I start cadence, when is...
View ArticleForum Post: Capture CIS Database setup using Orcale 11g
Hi, Can we setup Capture.ini file and DBC configuration file to link to database systems like Oracle 11g. Regards, Vinay
View ArticleForum Post: RE: Capture CIS Database setup using Orcale 11g
You will need to have an ODBC driver for the Oracle database, 32-bit for 16.x and 64-bit for 17.x, installed. Then configure a datasource through Control Panel for the database using the ODBC drivers...
View ArticleForum Post: Calibre LVS errors for a design generated in Encounter
Hello all, I made a design in SoC Encounter using NangateOpenCellLibrary 45nm. The layout had zero geometry and connectivity violations. I then needed to go to Calibre for LVS and PEX in order to do...
View ArticleForum Post: searching just one forum
It looks like the search on the upper toolbar searches everything . Is there a local search on this new website to just search one forum ?
View ArticleForum Post: RE: Calibre LVS errors for a design generated in Encounter
In Encounter, when I run this command "saveNetlist design.v -phys" I get this warning: No Power/Ground connections in top module (design). Pwr name (VDD). Gnd name (VSS). 1 Pwr names and 1 Gnd names....
View ArticleForum Post: RE: multi-technology simulation netlisting through command line.
Not as far as I know. Normally the MTS netlists are only produced when you actually simulate. To have some means to batch create the netlists would probably require an enhancement request. Regards,...
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