Forum Post: RE: ERROR: Netlister: unable to descend into any of the views defined in the view list

Hi Andrew, Exactly you are right. I put “verilogA” (uppercase A) in the view list because while creating cell “ADCon_16bit” with the help of cadence modelwriter, I have chosen “modelwriter” in ‘Type’ field just below ‘view’ field in the pop up window. Then after that I have just given necessary parameters for ADC converter like number of output bits, max voltage, min voltage etc. After that Verilog.va editor file pops up with the source code automatically and after saving file, a symbol generated. Now corresponding to cell “ADCon_16bit” two views are created: - one is ‘VerilogA’ and other one is ‘symbol’. My project description says that: I need to build a DC-DC buck converter with digital feedback control loop. So far what I have done is that: - DC-DC converter has 3 stages: - Power stage (having switching transistors), LC filter with load resistor and feedback control loop for generating variable duty cycle to control switching of power transistors. As per the project description I need to implement power stage and LC filter with load with schematic view having electrical components from defined library. But feedback control loop needs to be implemented in digital domain. As per many research paper, what I have read that digitally controlled IC in feedback loop for DC-DC buck converter has 3 major components blocks - (i) ADC converter (ii) programmable compensator based on Look-up tables (iii) Digital pulse width modulator (DPWM). Below are things I have done: (i) created top cell “dc-dc_conv” with view ‘schematic’. (i) Power stage with switching transistors instantiated in schematic window with L, C and variable load resistor R (design variable) (ii) for digital feedback control loop – (a) 1st block->>ADC converter created with cell” ADCon_16bit” through modelwriter with view “VerilogA” and “symbol” generated; (b) 2nd block->> PID compensator yet not created (I will create it in Verilog); (c) 3rd block ->> DPWM created with view ‘functional’ and corresponding symbol generated (source code is verilog). (c) 3rd block->> DPWM block created in verilog and symbol generated. Finally, I have created a ‘config’ view of my top cell ‘dc-dc_conv’ which populated all view of those instances which are in the top cell. I have selected simulator as spectre Verilog. Can you suggest which simulator needs to be invoked. Now there is no portioning error. I have populated both Analog stop view list and Digital view list and after that I have interface the instances in the top cell config view using Mixed signal opts->>verimix->interface instance. Also, I have changed the view to ‘veriloga’, now working fine. Now the error is in Verilog code which I need to fix. So basically ‘spectreverilog’ will do the work? Also can you suggest how to implement PID compensator in VerilogA or Verilog. Thanks, Rahul