Forum Post: RE: Allegro 17.2 backdrill solder mask export to GERBER
The pad size on the standard SOLDERMASK_TOP and SOLDERMASK_BOTTOM layers for Via and Pins will be enhanced based on the Backdrill Soldermask in the Padstack. This dynamic pad size change is done when a...
View ArticleForum Post: RE: Find a overlap of two layers if that layer present in PCell also
Mahesh, I agree with Lawrence - maybe this is a cultural thing, but (other than it not being standard outside of Indian English) it did suggest that you were expecting Lawrence (who doesn't work for...
View ArticleForum Post: RE: Incorrect component location on exported IDF
It seems that SolidWorks doesn't follow the IDF specification. Read the spec, see what PCB Editor sends to IDF and you should be able to prove by manual processing of the data for component location,...
View ArticleForum Post: RE: Incorrect component location on exported IDF
I should add that STEP data does seem to be processed correctly so some SolidWorks users have moved to using that format instead.
View ArticleForum Post: RE: ERROR: Netlister: unable to descend into any of the views...
Hi Andrew, Exactly you are right. I put “verilogA” (uppercase A) in the view list because while creating cell “ADCon_16bit” with the help of cadence modelwriter, I have chosen “modelwriter” in ‘Type’...
View ArticleForum Post: Constraining input signal in Encounter
I have a serial-to-parallel converter based on a shift register and a bank of flip-flops that latches the data out. I synthesized this in dc_shell and p+r in Encounter. My timing constraint file is...
View ArticleForum Post: RE: ERROR: Netlister: unable to descend into any of the views...
If you have Verilog views (i.e. digital Verilog) then you'd have to use a mixed-signal simulator. I would suggest you use "ams" as the simulator (you'll need an INCISIVE release installed), i.e. AMS...
View ArticleForum Post: RE: Incorrect component location on exported IDF
Thanks for the help. I'll do a deep-dive into the IDF data and make sure that it is correct.
View ArticleForum Post: RE: Incorrect component location on exported IDF
Hmmm...there were quite a few fixes made to IDF import in SW16 after about SP3. Right now using SW17 SP3 with no issue. If you want to post IDF here as ZIP would be willing to test with SW16&17
View ArticleForum Post: Marking nets in cadence showing shorts
HI , When I am trying to mark nets in cadence to verify routing i am am seeing shorts. Cadence version is IC6.1.7-64b-500.7 . Marking the nets is also highlighting other unconnected nets, but LVS is...
View ArticleForum Post: RE: Allegro 17.2 backdrill solder mask export to GERBER
The thing that it does not do it. That is why I posted this question. Maybe somewhere is an option to turn it on. In my project most of backdrills are on bottom so I am creating artwork with layers:...
View ArticleForum Post: RE: Marking nets in cadence showing shorts
Hi Anand, it realy depends how the shorts are created to solve that. What we usually see, is that MOS transistors are shorting nets via the common Drain-Source active area shape. If this is the case...
View ArticleForum Post: RE: Noise sources in PSS analysis
Hi ，I am not sure when you can see this message .I am a new beginner in IC desigen, Can i ask an question about VerilogA ？In the Veilog-A manual ,I see this code ,but i cann't understand what is kf,...
View ArticleForum Post: RE: A question about merge two PCB design in the same panel?
I have the same method to make multipanel. I create a modules of boards and I add the modules of new panel.brd. But there is problem with RefDes. Program adds a Prefix to repetitivie names. It is...
View ArticleForum Post: Allegro 16.6 Reports
Is there a way to get a report that contains pins that have thermals and what layers they are connected to?
View ArticleForum Post: RE: many part Number just one part reference in ORCAD CIS
I normally use Variants to generate the BOMs I need, my problem is how to have "different Part Number" associated to just one part reference in the schematic. I use also CIP-E with SQLEXPRESS used for...
View ArticleForum Post: RE: ERROR: Netlister: unable to descend into any of the views...
Thanks Andrew. It worked fine and now the "ams" simulator is able to partition the blocks which is in verilog a, verilog (digital) and schematic.
View ArticleForum Post: BindKeys for virtuoso advanced
Hi, I would like created a BindKeys advanced for my virtuoso environnement: hiSetBindKeys ( "Layout" list ( ; comment: I press "F1" one time I create a path with the value_1, I press "F1" two time I...
View ArticleForum Post: RE: Noise sources in PSS analysis
This isn't really related to the earlier post, and anyway the forum guidelines ask you not to post on the end of old posts. Please read the guidelines ! The parameters kf and af correspond to the...
View ArticleForum Post: RE: TO select all mosaics in visible area
Sampat, This will do it: cv=geGetEditCellView() bBox=hiGetViewBBox() foreach(inst dbInstQuery(cv bBox 0 0) when(inst~>objType=="mosaic" geSelectFig(inst) ) ) Andrew.
View Article