You might want to take a look at VerilogIn maps VDD, GND, tie Low 1'b0 and tie High 1'b1 nets to VDD! and GND! which are Global power and ground . However, in this case, your Verilog code is behavioural, so I'm not sure this is going to be terribly relevant since the behavioural code can't be changed to a schematic. Andrew
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