Forum Post: Challenge 7 - Simulation Setting
Hi, Question 1 in instructions for Challenge 7, we have Initial Solution: Vz=6 m/s Boundary Condition - inlet: Vz=23 m/s Should't they be equal to 23m/s ? Question 2 Boundary Conditions - Outlet:...
View ArticleForum Post: RE: steady solution as an initial solution to an unsteady...
hey, I found the mistake. Forget to implement a depence to the time. I will need OpenLabs to implement a boundary condition that changes with time or ?
View ArticleForum Post: RE: Challenge 7 - Simulation Setting
Question 1, also Vt is different, 1m/s in initial solution, 3 m/s in boundary conditions. Shall we use 3 overall?
View ArticleForum Post: Get pcell parameters with skill
I have defined a pcell with pcDefineParameters and add cdf to it. Now I'm looking for a way to get the pcell parameters (not the cdf), their name, datatype and default value. All the info I can find...
View ArticleForum Post: RE: Power supplies of standard cells
What do you have in the Verilog code? Are there power/ground pins? These options are intended to be global power/ground nets, and to replace any 'b1 and 'b0 values in the netlist with these global...
View ArticleForum Post: RE: Get pcell parameters with skill
cv=dbOpenCellViewByType("gpdk090" "nmos1v" "layout") foreach(mapcar param cv~>parameters~>value list(param~>name param~>valueType param~>value) This will open the PCell superMaster (of...
View ArticleForum Post: RE: Challenge 6: Error: Domain of Row 1: negative cells in the...
Passiert! Kenn ich :)
View ArticleForum Post: RE: Challenge 7: Simulations Auswertung fehlerhaft seit letzter...
Hi Konra, please excuse my late response. The y1 simulation should reach the convergence criterion of -8. The simulation y50 should not. I would suggest let's first check, if your grid seems to be...
View ArticleForum Post: RE: Challenge 7 - Simulation Setting
Hi Stefano, to question 1: Please use as initial solution the lower value with 6 m/s (and 1m/s for vt). This is on purpose. In general it is a good idea to be as close as possible to the final...
View ArticleForum Post: RE: change the working directory path
Hi Hussein, The OpenLabs module in Omnis 5.2 is included in the free student license provided that the system requirements for the use of OpenLabs are met of course. I'm not so sure having the .numeca...
View ArticleForum Post: RE: change the working directory path
How can I install the OpenLabs module. The email I received, or in the download area I see only omnis and fine marine. Yes I actually like your idea better too. T his means that I have to run the...
View ArticleForum Post: RE: change the working directory path
OpenLabs is part of Omnis. You can find the information how to access it in the Omnis 5.2 documentation under: OMNIS tools > Simulation > Optional models > OpenLabs > How to use OpenLabs...
View ArticleForum Post: RE: Power supplies of standard cells
Thanks for the response. Here is the code snippet module decoder ( input i_en , input [ 7:0] i_data, output reg [255:0] o_data ); always@(*) begin if (~i_en) begin o_data <= {256{1'b0}}; end else...
View ArticleForum Post: RE: Power supplies of standard cells
I saw one file named "powerpins.il" in one of course which I had. I am giving this file to space based digital custom placer. I am attaching that file here. I don't know how to add the command to...
View ArticleForum Post: RE: Power supplies of standard cells
You might want to take a look at VerilogIn maps VDD, GND, tie Low 1'b0 and tie High 1'b1 nets to VDD! and GND! which are Global power and ground . However, in this case, your Verilog code is...
View ArticleForum Post: RE: Power supplies of standard cells
[quote userid="499797" url="~/cadence_technology_forums/f/mixed-signal-design/56662/power-supplies-of-standard-cells/1388119#1388119"] saw one file named "powerpins.il" in one of course which I had....
View ArticleForum Post: RE: Power supplies of standard cells
The thing is I have synthesized the code using genus. Default supplies for standard cells are vdd! and gnd!. I imported the synthesized code to virtuoso and while importing the design global power...
View ArticleForum Post: RE: Wrong keyboard mapping
Hi Andrew, thank you very much for your answer. Actually CDE 1.6.10 is the Window manager on the Sun. 'xev' (executed on the linux server via ssh from the solaris box) delivers the correct keycode and...
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