At times PCB designers get confused looking at the serpentine traces on PCB boards and why they’re routed the way they are, especially in boards involving DDR memory interfaces. They wonder at what point they need to use this kind of routing and when they should be mindful about factors like propagation delay, dielectric material of pcb, stack-up etc.. Below are few points to consider before starting DDR routing: Dielectric Constant: The dielectric material of PCB influences the propagation delay of a signal because dielectric constant is directly proportional to propagation delay. The relation between dielectric constant and propagation delay (tpd) is given by, √Er/Vc ps/in, where Er = substrate dielectric constant, Vc = speed of light = 3x10^8m/s . Setup time: The clock lines are responsible for controlling the timing of data input and output from the memory. It is crucial that each bit of data on the data bus is received and stabilized before the clock cycle. To ensure this, the data bits may need to be present on the pins for a specific duration before the clock pulse arrives, which is referred to as setup time. Since DDR devices require this precise setup time, it is essential that the clock is designed to arrive at the exact moment needed. The only way to adjust the speed of arrival is by increasing or decreasing the trace length using serpentine routing strategy. Skew: It is the difference in arrival time between two signals due to unbalanced trace lengths. Everything should be clocked synchronously to avoid data loss. All bits should arrive from source to destination at the same time, that’s why length matching of all buses is very important in DDR routing. The Designer should look at the timing budget to know the skew limit he can afford. For instance, if there’s a skew budget of 585ps, then 150mm*0.585ns = 87mm is the length difference between the traces which the designer can afford to have minimal skew. The components that make up the board-skew budget include ISI (Inter symbol interference), VREF noise, path length mismatch, crosstalk, CIN mismatch and termination resistor tolerance. ISI : It is caused by cycling the bus faster than it can settle. Due to reflections on your PCB, you might have one bit from a previous data package interfering with the new data because of overshoot or undershoot reflections. Crosstalk : If the circuit routed signals are too close to one another, there will be coupling between them which leads to crosstalk. Crosstalk is caused when there’s no proper ground shielding between traces which leads to capacitive coupling. It is recommended to have a ground reference layer for every signal layer to minimize crosstalk. V REF Noise : Reference Plane noise and crosstalk are the two major contributions to VREF noise that causes strobe to data skew. VREF noise limits can be used to find worst-case skew. Minimizing VREF noise is very important aspect in designing DDR SDRAM. The trace should be as wide as possible to reduce the inductance on the line with 15 to 20 mils of spacing from adjacent signals while laying out VREF. Balanced decoupling capacitors should be placed as close as possible to the chip to reduce VREF Even if the designer has all these considerations in mind, there are still few other factors like return path, control impedance, Z-Axis delay, pin package delays which can affect DDR routing. You can take leverage of options such as SigXplorer, Signal Integrity/ Timing/Routing Constraints in Allegro X tools to design high speed PCB and achieve functional board.
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