Hi, I would like to probe 4sets of 8bit buses internal to a block (internal ADC outputs) from test bench level. At the test bench level, i will then be applying these bus voltages/signals to a veriloga block for further processing. Now, i am probing one internal net at a time using a deepprobe each by setting heirarchical node to ADC.DIG1\ on the deepprobe May I know if there is a way to probe the whole bus at once, rather than probing one net at a time. That could be something like setting heirarchical node to ADC.DIG1\ Thank you!!
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