My board has 12 layers. 4 layers of them can't be poured copper correctly. In the normal layer, the copper has correct clearance with pins/clines/vias: While in the abnormal layer, the copper only have clearance at the edge of the shape: I can confirm they are dynamic copper And the shape parameter has been set to smooth, no exception overrides: The 4 problematic layers have conductor layers and plane layers. In the constraint manager, they have same spacing settings: How can I resolve this?
↧