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Forum Post: RE: detecting process corner from within verilogA model

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Hi Saloni, thank you for your reply. Implementing the functionality in the verilogA model using the value of the parameter and if/else is clear. My question is how to pass the value from the "wrapper.scs" to the verilogA model? This is my file "wrapper.scs": library wrapper section NN parameters corner=1 include "gpdk.scs" section=NN endsection NN section FF parameters corner=2 include "gpdk.scs" section=FF endsection FF endlibrary wrapper This is my model "veriloga.va": `include "discipline.h" `include "constants.h" module inv(A, Y); input A; output Y; electrical A, Y; parameter real getcorner=1; // how to pass "corner" from "gpdk.scs" to "getcorner" of "veriloga.va" ??? endmodule When I instantiate the verilogA model (cellview name is "veriloga_read_corner") in the schematic testbench I press Q (properties) and set: CDF Parameter of view veriloga_read_corner getcorner corner But I get following error: nchelp ncelab CUBSPA ncelab/CUBSPA = Assigning a string value to a parameter which is declared to be either real or integer is illegal. In summary, what I am missing is how to pass the parameter value "corner" defined in "wrapper.scs" to the parameter "getcorner" inside the "veriloga.va" model. Thank you very much for your help.

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