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Forum Post: RE: detecting process corner from within verilogA model

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I just tried this on a small testcase and here's what I had to do. When you run netlisting from ADE, do you get a design variable called 'corner' added to the state? You can give the default value to 'corner' in ADE state e.g. 1, and then run the simulation. Spectre will then see variable corner being defined more than once, so depending upon your setup, you might get an error for the same parameter being defined twice. To get past that error, you can set Simulation option redefinedparams=warning. The value coming from models will override the value set in ADE. Hope this helps. Regards, Saloni

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