Forum Post: Plotting transistor operating point components in DC simulation
Hello, I am using Cadence Virtuoso IC6.1.5-64 bit and ADE Spectre Version 11.1 2012 I am trying to plot different operating point components of the MOS transistor (gm, region, vth,...etc). In my simple...
View ArticleForum Post: RE: How to Extract segment length info from Constraint...
The information you are requesting is available directly from Allegro, the skill access to data in Constraint Manager is extremely limited IMHO Below is some example skill code that will report the net...
View ArticleForum Post: RE: Running multiple PAC simulations on the same PSS analysis
The PPV is for the voltage source at net GATE_IN. Though, the oscillator output voltage is almost sinusoidal, the PPV for the voltage source (unlike the PPV for the current source at net VOUT_M) is...
View ArticleForum Post: RE: Running multiple PAC simulations on the same PSS analysis
Also, I think, for HB analysis we can not get 70 PXF sidebands without having 70 harmonics for PSS.
View ArticleForum Post: RE: problems opening STEP file in solidworks
in allegro,i cant do stepexport with external copper, i open that step file in solidworks means i cant see a pcb ,but all components visible to me,, for that problem any solutions are there...
View ArticleForum Post: Assura41 undefined function - pcDefinePCell
Hi I am writing LVS extract file for our own technology, however , the assura41 seems keep showing error information Error eval : undefined function -pcDefinePCell after that error message loadng...
View ArticleForum Post: Import->logic(cadence)
Hi All, A warning appeared after I import -> Logic. #1 WARNING(SPMHNI-192) : Device/Symbol check warning detected. [help] WARNING(SPMHNI-161) : Symbol changed for 'DIE'. Pin edits were lost. I've...
View ArticleForum Post: RE: command to find the maximum and minimum drivestrength of a...
Hey, can you help me with TCL script to fix DRV violations?
View ArticleForum Post: RE: Assura41 undefined function - pcDefinePCell
seems the generation of {circuit}.sdb was failed, however, the cdl generation was correct. I have added auLvs in cdf~>SimInfo
View ArticleForum Post: Liberate : generate lib file for a level shift cell
Hi, Did anyone generate the lib file for a level shift with liberate? I don't know how to make some settings. (1) For the following netlist, .SUBCKT ls_cell IN OUT VDDH VDDL VSS *.PININFO IN:I OUT:O...
View ArticleForum Post: Shifting routes and placements from one board to another
I am working on a high speed design and i do have its reference design and layout with me. I have made some changes in the reference design and now i want to export it to PCB. I want to ask is there...
View ArticleForum Post: RE: Assura41 undefined function - pcDefinePCell
The most likely explanation is that you have SKILL code in your libInit.il (or loaded from the libInit.il) which is attempting to recreate a PCell by calling pcDefinePCell. You should not do that (and...
View ArticleForum Post: cell list excluding few devices from one category
Hello I am using list~>cells ~>name to get the cell list.This cell list gives the whole list of cells coming from one library. I would like to exclude few cells coming from category in this...
View ArticleForum Post: RE: Liberate : generate lib file for a level shift cell
Hi Fengye, you need to use set_pin_vdd/gnd to tell the tool the different pins and their associated power domains. Regards, Guangjun
View ArticleForum Post: Get from which lib a cell is from
Hi, I am doing some scripting to manage some files and what I have in my hands is a bunch of cell names that are spread across some libraries. What would be the best way to find from which library the...
View ArticleForum Post: RE: Liberate : generate lib file for a level shift cell
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V0000091BSOUA2&pageName=ArticleContent I found this article in our database.
View ArticleForum Post: RE: Schematic Symbols: How to hide pins on 17.2 S057
Thank you so much Nitin. That's exactly what I needed. Not sure how I missed it. Perfect, thank you.
View ArticleForum Post: RE: Get from which lib a cell is from
Hi Rodrigo, A cell name for itself is ambigous - you can have one and the same cell name in different libraries. If you want to know in which library a given cell name is contained you might go like...
View ArticleForum Post: RE: Liberate : generate lib file for a level shift cell
Hi, Guangjun, Thanks for your reply! The volatage net incudes VDDH, VDDL. I use " set VDD_VALUE 1.20 set VDDS_VALUE 0.60 set_pin_vdd -supply VDDH ls_cell OUT ${VDD_VALUE} set_pin_vdd -supply VDDL...
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