Forum Post: RE: Need to reduce the height of a particular text layer inside...
Thanks Andrew, I understand your reasoning. I'm in the middle of writing code to the migration of a full chip design from one foundry to an other, and things like this will happen a lot in the code I'm...
View ArticleForum Post: RE: How to create autocomplete text strings?
[quote userid="395537" url="~/cadence_technology_forums/f/custom-ic-skill/42826/how-to-create-autocomplete-text-strings/1363694#1363694"]FindSourceLibrariesCB[/quote] This is the procedure where the...
View ArticleForum Post: RE: Move a trace - The Polygon FILLS IN
No it's fine, the shape is becoming Non Dynamic you can simply go to Display - Status (or Check - Design Status if using OrCAD) and click on update to smooth. Whilst you are there check the Dynamic...
View ArticleForum Post: RE: How to create autocomplete text strings?
Hi Sjoerd, Thanks for the good starting basis for this - very helpful (great to see somebody else volunteering code for others to use!) BTW, for your specific example you can use...
View ArticleForum Post: RE: How to append a plot from a .csv file on to an already...
I don't see that. What version are you using? Andrew
View ArticleForum Post: RE: Change print paper size
I've contacted them. thanks for the help though
View ArticleForum Post: RE: Spectre MDL help for "noise" analysis
Got help from Cadence support: alias measurement runnoise { export real input_noise, output_noise, rms_output_noise, rms_input_noise; run noise(start=1, stop=1G, dec=10, iprobe=V7, terminals={"OUTP"})...
View ArticleForum Post: Ask for help about the check pad/via overlap with the text
Hi all , now I have wrote a code to check if the pad/via overlap with the text ,but it always return"Total of text on TOP pad:0" Could you help to check and give some advice, thanks in advance! Code...
View ArticleForum Post: RE: Ask for help about the check pad/via overlap with the text
My idea is as following: first get the bBox of pin/via ,then judge if the regular pad or solder is bigger , then judge if the bigger bBox area exist a text , if have text , then highlight the text.
View ArticleForum Post: RE: Ask for help about the check pad/via overlap with the text
Whatever else this code is doing, cnt isn't being incremented. Add cnt++ before or after axlHighlightObject
View ArticleForum Post: RE: Ask for help about the check pad/via overlap with the text
Thank you eDave! This is my mistake. There seems also have other wrong place.When code run finished , return "Total of text on TOP pad:0" , and all pin/via highlighted.
View ArticleForum Post: Drain Current Noise Power VS gm
Hello all, I tried to extract drain current noise power at 6 GHz of a single NMOS transistor in order to plot PSD versus gm under different channel width. I'm doing with hb and hbnoise while it seems...
View ArticleForum Post: RE: Drain Current Noise Power VS gm
You need to use probe and select the instance to measure the current through. This could be a resistor, but since you don't want a resistor, place an iprobe from analogLib in series with the drain and...
View ArticleForum Post: Unable to increase thickness in waveforms of type "bar" in ViVA.
Hi, IC.6.1.7-64b.500.13 Is there a way to make the plots of style (or type) "bar" stand out more than they do when printed? I see that the width or style (dash, dot, etc) properties do not have any...
View ArticleForum Post: RE: Optimization method in ADE_XL or ADE_GXL
Dear Andrew, I have read the documentation help about cadence optimization tool. I have some questions please which I couldn't find the answer after reading the document I have a question about...
View ArticleForum Post: RE: How to append a plot from a .csv file on to an already...
The virtuoso version is sub-version ICADV12.3-64b.500.23 The spectre version is sub-version 18.1.0.335.isr6
View ArticleForum Post: RE: Optimization method in ADE_XL or ADE_GXL
By the way, The document you thankfully gave to me ( Session CUS12 : Using Virtuoso® ADEGXL Circuit Optimiser to Reduce Time-to-Market for Complex Analog Circuit Design in 40nm )is not valid any more,...
View ArticleForum Post: RE: Ask for help about the check pad/via overlap with the text
I ran your code thru the checking utility sklint & corrected the issues it found, corrected a couple of logic issues and added a couple of debug printing statements, please try using the updated...
View ArticleForum Post: RE: Optimization method in ADE_XL or ADE_GXL
The link still works - perhaps it was a temporary problem? I may not have time to answer the other questions before I go on vacation tomorrow evening though... Andrew
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