Forum Post: RE: Symbol editor missing property sheet tab/drawer
So, if you select one of the pins, the 'Pin Editor' doesn't come up? That would be very odd. Are you 'single clicking' the pins, or 'double-clicking' on the pins? Mine always pops up.
View ArticleForum Post: RE: Symbol editor missing property sheet tab/drawer
Yeah , i found out after i posted this , that the hotfix we have at the company is 037 and that feature was introduced in hotfix 038.
View ArticleForum Post: Re : Planarity of ATE socket Mounting & Donut pad of socket
Hi , Can anyone explain the purpose of maintaining "planarity" for ATE test socket and purpose of Donut pad?
View ArticleForum Post: RE: Re : Planarity of ATE socket Mounting & Donut pad of socket
ATE Test sockets for production use are expensive. If this fixture is used for testing over temperature range, the pcb usually falls apart(delamination) in six months from being cycled from 0 to 130...
View ArticleForum Post: RE: How to set a custom via as default via on VXL/GXL?
Hi Perry, One way to do is to save all the options into "~/.cdsenv" file. So you don't have to repeat the above steps every time when you open a new layout. To save options into .cdsenv file. Go to CIW...
View ArticleForum Post: Cannot EDIF out
Hi, I tried to edif out an inv schematic in library test which contains all devices in inv. But edifout.log shows "Error : Failed to open library test -- exiting". However, I succeeded edif out from...
View ArticleForum Post: RE: Cannot EDIF out
I copied analogLib to a new library analogLib_test, and did the same edifout process but failed. Comes out the same error message "Error : Failed to open library test -- exiting"
View ArticleForum Post: RE: Cannot EDIF out
Please contact customer support - it’s going to be very hard to debug this without seeing your data and setup. Unfortunately the error messages given by the EDIF interface are not very detailed so...
View ArticleForum Post: RE: Problems Generating allegro netlist from orcad schematic
These projects also allow students whose learning is deficient in one or more areas to escape practicing what they are not good at as more successful students will pick up the slack....
View ArticleForum Post: malias function
Hi, Does ADEXL has the "malias" function as in HSPICE? Ex: .malias nch = nch_mvt (I want to change all 'nch_mvt' in the schematic to 'nch' without modify schematic ) thanks.
View ArticleForum Post: Select vias GND
Hello, I'm working with ORCAD PCB 17.2. I would like to select all the vias on the net GND. Please could you help me. Many thanks
View ArticleForum Post: Select VIAS on a same net
Hello, I'm working with ORCAD PCB 17.2. I would like to select all the vias on the net GND. Please could you help me. Many thanks
View ArticleForum Post: RE: malias function
Your question doesn't really make sense. ADE XL is not a simulator. Spectre (which is a simulator) does support model aliasing, and you can do that either with the SPICE syntax: .malias nch=nch_mvt or...
View ArticleForum Post: RE: Select VIAS on a same net
Use the Find by Query function. In the Find pane click on Find by Query form choose Vias then net and pick the net you are interested in the results are shown in the bottom of the form, if you click...
View ArticleForum Post: RE: CADENCE IC STUDENT VERSION/TRIAL VERSION
Hello Tom, Is there any chance for a German university to join the program? I'm in charge of out new Design project at Universität Leipzig and need to create an international based program using at...
View ArticleForum Post: RE: CADENCE IC STUDENT VERSION/TRIAL VERSION
Tom isn't with Cadence any more, but the general way for European Universities is via the Europractice scheme here: http://www.europractice.stfc.ac.uk/membership/membership.html I'll forward this to my...
View ArticleForum Post: RE: Select VIAS on a same net
Hi Steve, Many Thanks for your reply. I have installed the hotfix SPB17.20.056 to have access to "Find by Query". It works and fully reply to my need!! Best regards
View ArticleForum Post: Set Subwindow ID for each Trace / Waveform
Hello, I am working with IC 6.1.8. After a transient simulation in ADE Explorer, where I have defined several outputs (signals and expressions), all signal-waveforms are plotted in the same subwindow...
View ArticleForum Post: RE: Set Subwindow ID for each Trace / Waveform
In IC6.1.8 with Explorer and Assembler, you can plot the graphs automatically, and then rearrange as you prefer into different sub windows. Then in ADE in the Results tab click on this icon: Give the...
View ArticleForum Post: genus include `define file
I have a file that list all the `defines that is used in the current design. This file (define.vh) is generated, like so : `define MACRO_1 5 `define MACRO_2 1'h0 ... etc But in genus when I run the...
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