Forum Post: RE: Re : Planarity of ATE socket Mounting & Donut pad of socket
Planarity mainly refers to the flatness expected under the socket (the top side of the PCB). This is kind of a carry-over from the old mechanical mentality whereas the mechanical engineer would want...
View ArticleForum Post: Component Device Pin Number Mismatch; Cannot Replace
Hi All, I have been trying to translate a board made in Altium to OrCAD. When making the Netlist, I received the warning: #3 WARNING(SPMHNI-184): Device library warning detected. WARNING: U11 component...
View ArticleForum Post: RE: Select vias GND
on the fidn filter you need to open "Find by query" then set up the filter and save the query as shown below. when you select the object, you check "By Saved Query" and select the one created. in my...
View ArticleForum Post: RE: Component Device Pin Number Mismatch; Cannot Replace
Obviously the Altium part is 'pin labelled' different than the Orcad footprint. The Altium netlist should be editable (e.g. text file), so look up U11 in the file and see what they label the pins as...
View ArticleForum Post: RE: Component Device Pin Number Mismatch; Cannot Replace
As far as I can see, the names are identical. I even have the original schematic library source. They are all the same. The PCB footprint is somewhat different. Altium named the 4 pins 1, 2, 3, and 2....
View ArticleForum Post: RE: Cannot EDIF out
I encountered the same problem and I don't know how to solve it
View ArticleForum Post: RE: malias function
I use Spectre as simulator. I want to know where to set "spectre syntax: model nch_mvt nch" in ADE XL. For HSPICE, I just simply put " .malias nch=nch_mvt" in my .sp file.
View ArticleForum Post: RE: Allegro Physical Viewer Crashed During Review
Even I am facing the same issue, Did you get any reply or solution from cadence team?
View ArticleForum Post: RE: Placing and routing identical circuits in PCB
what i usually do is to export the routing with the component as a sub-drawing and then import the sub-drawing into a different location in the same file i am working on.
View ArticleForum Post: RE: CADENCE IC STUDENT VERSION/TRIAL VERSION
Hello Stanley, I'm University Program Manager for EMEA at Cadence. Please contact me on my email address aklotz at cadence.com. Then we can discuss, if Europractice is the right choice, or direct...
View ArticleForum Post: RE: malias function
Create a file called (say) alias.scs and put: model nch_mvt nch in that file. Then add this file via Setup->Model Libraries in ADE (for the test) or Setup->Simulation Files under Definition...
View ArticleForum Post: RE: Select vias GND
Hi masamasa, Many thanks for your help!! It works. Best regards
View ArticleForum Post: RE: genus include `define file
You can parse your define.vh, convert it to a single string, and put it into the -define option of read_hdl command. Assume you have a file consist of only `defines. For example: `define SYNTHESIS...
View ArticleForum Post: Dump a Verilog Code in Cadence Virtuso.
I have a verilog code. I want to dump the code in Cadence Virtuoso and use the instance in my design. what is the procedure for it?
View ArticleForum Post: RE: Dump a Verilog Code in Cadence Virtuso.
I moved this to a more appropriate forum (the Feedback, Questions and Suggestions forum is for issues with the forum itself and not for technical questions). If you have some Verilog code, you could...
View ArticleForum Post: ADE EXPLORER - use existing netlist
I want to run simulations without Explorer creating a new netlist, but it doesn’t seem keen. I thought hitting run instead of netlist and run was sufficient, but it re-creates the netlist every time. I...
View ArticleForum Post: RE: Dump a Verilog Code in Cadence Virtuso.
Yes I have done that. But I dont know the proper process because I am new in Virtuoso. If possible send me the detail process how to create. thank you.
View ArticleForum Post: RE: ADE EXPLORER - use existing netlist
The input.scs will be recreated, but the file called netlist should (normally) be only recreated if anything in the design changes (it's assembled out of netlists of each subckt, which are...
View ArticleForum Post: RE: Dump a Verilog Code in Cadence Virtuso.
Rather hard to know what exactly didn't work (or even if it did work) because you gave so little information. You could also read the documentation (hit the Help button on the...
View ArticleForum Post: RE: ADE EXPLORER - use existing netlist
Hi Andrew, The reason I'm needing to do this is to identify which parasitic capacitance are the ones responsible for coupling undesired signals into our analog chain. By removing/changing individual...
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