Forum Post: RE: Help for Regular Expression, thanks in advance!
Thank you, Bram, My thought is immature. Now, I know how to do it after read your code. Thank you very much for your help. Thanks:)
View ArticleForum Post: Verilog $random seems to be not random
Hi, I want to generate a random number between -1 and 1 in Verilog-A by using "$rdist_uniform" or "$random", but the behaviour is not as I expect it. My code is something like: @ ( initial_step ) begin...
View ArticleForum Post: Regarding deleting X-Net property added for a signal in PCB board...
Hi, Iam using 17.2version Venture pcb design tool. I need to delete an X-Net property which had been added for a particular net. Can you guide me on fixing this issue.
View ArticleForum Post: Trouble using pPar with Spectre simulation
Hi everyone, I'm fairly new to Cadence so I'm sorry if this is easily solvable. I am trying to generate a symbol with a variable parameter. For instance, I have an inverter with the NMOS width set to :...
View ArticleForum Post: Unreasonable numbers and contributors seen in ADE-L Spectre noise...
Hello Everyone, I am having trouble of late trying to print out noise summary reports following a Spectre noise analysis. The following problems seem to show up: 1) Noise contributors aren't printing...
View ArticleForum Post: RE: Error during ADE spectre simulation
Thank you Andrew for your suggestions, I have contacted the PDK company, they fixed the issue for me, there was some missing files of the model which I then included. Now models are defined correctly...
View ArticleForum Post: RE: Unreasonable numbers and contributors seen in ADE-L Spectre...
Hi Vivek, Have you turned on the "Noise Separation" checkbox at the bottom of the noise "choose analysis" form? If so that breaks (or at least it used to; I've not checked the current status) the noise...
View ArticleForum Post: RE: Unreasonable numbers and contributors seen in ADE-L Spectre...
Hi Andrew, Indeed, that seems to have been the problem. Disabling the "Noise Separation" option resolves my problem entirely. Thanks so much. Regards, Vivek
View ArticleForum Post: RE: Placing and routing identical circuits in PCB
Thank you so much for all the replies guys, really appreciate it.
View ArticleForum Post: RE: Donut pad and shapes transparency
If you want to find an effective online grammar check it will be good for you to visit the website of the expert writing services.
View ArticleForum Post: RE: Verilog $random seems to be not random
Okay, I found that (for whatever reason) it works when I place the seed variable outside of the for loop: @ ( initial_step ) begin seed=32134 for (1=0; i<10; i=i+1) begin myvar[i]=...
View ArticleForum Post: RE: Regarding deleting X-Net property added for a signal in PCB...
Use Edit - Properties (set the Find Pane - Comps) and select the discrete part that the xnet is part of and add a no_xnet_connection property with a value of True to that part. Once applied the xnet...
View ArticleForum Post: calcVal with temperature sweep
Hi, I have 3 tests I want to run. The first test is a calibration that I run at just 50 degrees. Test2 and Test3 are the same but with different input current, both are swept across temperature. In...
View ArticleForum Post: RE: Error during ADE spectre simulation
Dear Andrew, after waiting for a longer time I could receive these messages I have seen similar problem and a reply from you like to solve it by First you might want to start by putting:...
View ArticleForum Post: RE: Error during ADE spectre simulation
Dear NorNand, [quote userid="428630" url="~/cadence_technology_forums/f/custom-ic-design/43017/error-during-ade-spectre-simulation/1364313#1364313"][/quote] I tried the above solution but still,...
View ArticleForum Post: RE: Unable to map design without a suitable latch. [MAP-3]...
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View ArticleForum Post: Unable to descend into any of the views defined in the view list,...
Hi, When performing the LVS , I am getting this error. ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'auCdl schematic', for the instance 'output_1_reg[0]' in...
View ArticleForum Post: Dots instead of solid lines when plotting corners
Hi all, I've started encountering a problem with corner plots. I usually can plot a value across corners, and it connects the dots into a line. Right now I just get separate dots. It seems it just...
View ArticleForum Post: Visibility,options,find tabs anchoring
Hello all, I vaguely remember able to anchor the three tabs ( Visibility,options,find ) in the style below: However I cant seem to get this going in my version of allegro 17.2, Currently the visibility...
View ArticleForum Post: RE: Dots instead of solid lines when plotting corners
Dear Roman, [quote userid="453210" url="~/cadence_technology_forums/f/custom-ic-design/43069/dots-instead-of-solid-lines-when-plotting-corners"]I usually can plot a value across corners, and it...
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