Forum Post: RE: open loop closed loop link via STB loop gain
i understand. Thank you very much.
View ArticleForum Post: RE: ERROR - [SPMHOD-29] in Allegro Tool
This is the classic "another designer is running a newer version of Allegro/Orcad than what you're using. You need to have a more current version running to load that file. For example - if you're...
View ArticleForum Post: RE: How to indicate off-board connections in LAYOUT
Classic - Make one net VCC1 and the other VCC2, and on the schematic place a NOTE saying in essence - "VCC1/VCC2 are common VCC. This connection is intended for an external power supply (+5V, or...
View ArticleForum Post: RE: OrCAD Capture V17.2 - BOM configuration management
The CIS Variant feature in Part Manager is your friend. Especially with "Variant View" that can highlight affected parts (might want to change the gray color to something more visible.) CIS allows you...
View ArticleForum Post: RE: OrCAD Capture V17.2 - BOM configuration management
"non mounted"? Don't you mean DNI? Add the property NOTE and add DNI for your non-mounted components. Variant works pretty well for this activity.
View ArticleForum Post: RE: Concept doesn't remember reference designators when I import...
Have you tried "Accessories->Transfer Occ. Prop. to Instance"? This pushes the PCB layout assignment into the schematic "logical" view so it can be reused with the updated references. Post back if...
View ArticleForum Post: Soldermask Swell...
I sometimes come across designs from the US where the tradition seems to be that soldermask dimensions are the same as the copper pads and that the board fabricator performs the swelling. Is there any...
View ArticleForum Post: Ocean: exporting internal circuit signals taking more than 1h
The following working code saves the voltage of all signals from a circuit in a text file: I0.U94.net0158 0.999999 ADDR_OUT\ -3.61176e-07 ADDR_OUT\ -3.68596e-07 ADDR_OUT\ -0.000613136 The problem is...
View ArticleForum Post: PSPICE Simulate only one page in OrCAD 17.4
Hello, I'm trying to run a PSPICE simulation on my schematic in OrCAD Capture 17.4, but i only want to do it on one page of the schematic, not all of them. I've associated SPICE models to the necessary...
View ArticleForum Post: Display NetGroup Definition Name On Net Alias
Is it possible to remove the Netgroup Definition from the Net Alias. I though this switch would work. Ex.: Netgroup: Test Members: Dat[0..1], RAS, CAS Test .Dat0 Test. Dat1 Test. RAS Test. CAS Would...
View ArticleForum Post: RE: How to indicate off-board connections in LAYOUT
I was thinking along those line as well. The issues that I see are: 1) VCC comes in, basically, on the 4 corners of the PCB. I had a general idea how I wanted to lay the board out but the VCC source...
View ArticleForum Post: RE: Simulation failed, cannot compile ahdl libraries
hi Andrew , I have a similar problem for the 64 bit OS would you please help me? Created directory input.ahdlSimDB/ (775) Created directory input.ahdlSimDB//bsource.va.bsource_1.ahdlcmi/ (775) Created...
View ArticleForum Post: RE: DNL/INL Using Cadence ahdlLib blocks for ADC
HI Andrew, Thanks for you help. What are the recommandation for the slope ramp ? For example an 8 bit adc over 1.2V range and 12M sampling ? It should be 56.25e3 V/s ? 1.2/(256*1/12M) or slower ? A RAK...
View ArticleForum Post: Two part functional symbol in Virtuoso
Hi, Does Virtuoso have method to support two part symbols? An example would be a relay with a switch and control symbol that is separated but bound to one functional model. This is supported in Allegro...
View ArticleForum Post: Export to PDF no longer working in Capture CIS 17.2
When I try to export to PDF from Capture CIS, the session log shows "(::capPdfUtil::printPdf) Generating PDF file from postscript ...." but no file is ever generated. This function was working...
View ArticleForum Post: VHDL-AMS delayed attribute
Dear all, I am currently trying to model a simple delay in VHDL-AMS. entity DELAY is port( terminal vin : electrical; terminal vout : electrical ); end DELAY; architecture behavioral of DELAY is...
View ArticleForum Post: RE: Avoid exporting .gi signals in Ocean
Dear zaratustra, [quote userid="338342" url="~/cadence_technology_forums/f/custom-ic-design/43315/avoid-exporting-gi-signals-in-ocean"][/quote] Question) Is there a way to avoid these ".gi" signals...
View ArticleForum Post: RE: DRC error: Mechanical Drill Hole to Pin spacing
Have you checked the constraint modes under mechanical spacing? That is the default value. Turn them off.
View ArticleForum Post: RE: How to indicate off-board connections in LAYOUT
That's fine. Use LDOs at each corner instead too. :)
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