Forum Post: RE: What is the Assembler equivalent of loading save output state...
Thank you for the suggestion Andrew. I want to follow this topic. my site: couponplay
View ArticleForum Post: Genus: Problem with long module name due to parameter types
Hello, I'm currently synthesizing a SytemVerilog design using Genus 19.11. In the report, I'm getting the information, that there is one subdesign with a long module name. It turned out that this long...
View ArticleForum Post: RE: how to set flight line that is just indicating the...
I checked with R&D, and the validated enhancements were for a internal project that was just a prototype of how this might work, not the final implementation. That's not planned at the moment, but...
View ArticleForum Post: RE: Frozen Innovus GUI while executing Tcl script to highlight...
Hi, instead of waiting on stdin to pause the script, you can do while {![eof $fid]} { ... suspend } Then type resume to continue with the loop.
View ArticleForum Post: Just some pcell info
I have done some small pcells in layout, but is the difference or defines a pcell for schematics?? What are some of the things to be aware of when doing schematics pcells?? Paul
View ArticleForum Post: RE: Just some pcell info
Paul, Of course generating schematic PCells with PCell Designer is easier (see Generating a Schematic Parameterized Cell using PCell Designer ) but if you're going to create them using SKILL, the key...
View ArticleForum Post: RE: Allegro 17.4 always reports new files as created in 17.2
Thank you!!! This answers my question and makes sense. I have seen other forum comments (and perhaps even some Cadence documentation) that states anything saved from 17.4 tools is saved as 17.4, so...
View ArticleForum Post: Changing schematic properties and callbacks
Hi, I am in the process of evaluating a new PDK and I would like to run some sweeps for different geometries and device types. The issue with sweeping "the standard way" is that this substitution...
View ArticleForum Post: RE: How to move specific file from one directory to another one
Robin, There's no built-in function to find the directory part of a file name (unfortunately) so you'd probably do something like: fileTailPattern=pcreCompile("/[^/]*$")...
View ArticleForum Post: Assura DRC for Dummy Fill Generation
I'm trying to generate auto-fill patterns using Assura DRC. Below is the sequence that I'm thing about: 1. scan the whole chip and divide up into pieces. 1) find the rectangluar spaces that can fit...
View ArticleForum Post: RE: Where can I find the meaning of each parameter of the DC...
Without seeing the models, I'm guessing that the model uses the "bjt" device in Spectre. If you run (from the UNIX command line): spectre -h bjt then scroll to the Operating Point Parameters section,...
View ArticleForum Post: RE: pcell streamout with different cell name
The cell names are not the same - I don't understand what you mean? The stream file contains an instance of crtmom_CDNS_0 and crtmom_mx_CDNS_0 - these are clearly different . The fact that the...
View ArticleForum Post: RE: Assura DRC for Dummy Fill Generation
Probably best to discuss this with customer support (I can only give a quick answer here - maybe others can help though), but the first step would be to read the various approaches for doing fill...
View ArticleForum Post: DFT expression results each in separate subwindow in ADE Assembler
I have 20 or so DFT expressions that all plot in the same subwindow when I use ADE Explorer. This is handy to quickly compare the magnitude of each. When I switch to ADE Assembler, each is plotted in...
View ArticleForum Post: RE: How can I generate schematic of standard cell using standard...
Example: devSelect := nfet nmos2v propMatch := subtype N devSelect := pfet pmos2v propMatch := subtype P You may refer more by clicking the "Help" button at the bottom of the form.
View ArticleForum Post: RE: DFT expression results each in separate subwindow in ADE...
Chris, Bizarrely I don't think I'd noticed this behaviour before. I did some searching and originally it was related to the fact that in ADE XL you would commonly be sweeping variables and/or corners,...
View ArticleForum Post: RE: Assura DRC for Dummy Fill Generation
Thank you, Andrew for your comment. I will ask customer support. But I will still appreciate any answers from other users here.
View ArticleForum Post: RE: Changing schematic properties and callbacks
Michele, I'd suggest you either: Use the parameters capability in ADE Explorer/Assembler (or even XL) which allows you to sweep the parameters of a device and the callbacks do get fired in the...
View ArticleForum Post: RE: DFT expression results each in separate subwindow in ADE...
Thanks for the suggestion, Andrew. I was thinking I'd have to create the template in Assembler, but you're right, it would be a lot easier to do it in Explorer and switch back. Cheers, Chris
View ArticleForum Post: How to resurrect Virtuoso schematic and export
I have Virtuoso schematics of a "digital" design (down to transistor level) I created 10 years ago, and last looked at 5 years ago. That represents the only times I've tried to run Virtuoso in the...
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