Forum Post: IQ cross-talk: simulation artefact?
Hi, I would like to simulate I/Q crosstalk in my system (and specifically assess whether I can use 50% duty cycle which is known to be problematic for I/Q crosstalk because two branches are used at the...
View ArticleForum Post: Cadence tool to generate .lib file for Analog modules
Hi, Please tell me which tool is available in cadence to generate a .lib file for Analog modules. I have seen some old posts on the same but clarity is not there whether it is specific for analog....
View ArticleForum Post: HOW TO ADD VOID TEXT IN COPPER POUR
IM IMPORTED A LOGO. It should be placed on top copper pour. but logo text not containe copper (void). INVERTED TEXT CREATION.
View ArticleForum Post: RE: FGC adding MinMax Voltage panic!
Don't Panic! :-) from what i can tell, this message was some extra debugging info that should not have been getting printed out to the log. it seems to be fixed in 16.20. So I think you can ignore it.
View ArticleForum Post: find warnings / marks on the layout view using SKILL
Dear all, I have numbers of PCell on my layout view, and some of them have markers with warnings, is there a SKILL way to detect such markers? cv~>markers gives nil Ideally, I want to find to which...
View ArticleForum Post: RE: is there a way to see changes on layout in real time?
Sorry, it is not. I've asked Cadence in the past to provide the objects that are traced by Mark Net so that similar functionality could be created, but I'm not aware of any built in functionality to do...
View ArticleForum Post: RE: find warnings / marks on the layout view using SKILL
Hi Vadim, Assuming that you have the variable 'inst' set you can see the failure marker using something like the following: exists(shape inst~>master~>shapes shape~>theLabel ==...
View ArticleForum Post: RE: find warnings / marks on the layout view using SKILL
It depends what kind of "markers" they are. It could be inst~>master~>markers - or it could be the kind of label (or shape) on the marker/warning or marker/error layer (this is the old way...
View ArticleForum Post: RE: HOW TO ADD VOID TEXT IN COPPER POUR
I don't do any logos/symbols as text objects, but as shapes. Then I know the font is going to be correct. I prepare a DXF file from whatever format I have in Inkscape - convert everything to paths and...
View ArticleForum Post: How to store a value/Store function in Verilog-A/AMS
Hello guys, I have been looking for a storage element or something like that (in Verilog-AMS/A) so that I can keep the output value of my circuit forever, after one-time simulation. I think it is very...
View ArticleForum Post: RE: HOW TO ADD VOID TEXT IN COPPER POUR
I have a Skill solution for importing and scaling graphics. Search for logoMaker_public on the Skill forum or contact me if you want a copy.
View ArticleForum Post: RE: How Can Utilize a dwindow in the same fashion as an Assistant...
Sort of. It has a nice example of changing out the contents of a form in a dockable window. That's pretty useful. I still can't seem to get this new dock window to show up in the window->assistants...
View ArticleForum Post: Need help in identifying pending Objections in Specman
Hi, One of my Specman tests hangs in simulation because one of the component units that raised Objection did not drop it correctly. I was able to find out approximately which instance did that using...
View ArticleForum Post: RE: Launching PVS LVS/DRC results browser from a skill file
Thank you Andrew. I have filed a CCR #1733361 for anyone else interested.
View ArticleForum Post: RE: Hide bias voltages
I found a workaround - make a copy of the .dsn file (in windows explorer), then open it in orcad and select it to be a psice project. Now pspice>bias points>enable is no longer greyed out. Not...
View ArticleForum Post: RE: How to place IO pins on internal wires and bumps in Innovus?
You can place IO pins inside block by using editPin -side inside option.
View ArticleForum Post: RE: Error while simulating verilog-A block
Thanks for the reply. My error has been resolved. It was because of missing of 32 bit version glibc-devel package. Thanks for assisting
View ArticleForum Post: RE: Cadence tool to generate .lib file for Analog modules
We have Liberate AMS which is for characterisation of mixed-signal modules. I assume that's what you mean, because a .lib for a pure analog block is probably of limited value... For Liberate AMS I...
View ArticleForum Post: RE: IQ cross-talk: simulation artefact?
It's not clear what exactly you're simulating here or how you're analysing the results, so please contact customer support so that you can supply the design details (ideally the netlist and everything...
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