Forum Post: RE: Verilog A code with lookup table
Hi Andrew, With isolines it works fine. My problem is when there is just one value (like 11.85 10.84 -1.73E-06. There is no value other than y=10.84 for x=11.85). Can $table_model just return the...
View ArticleForum Post: RE: Changing the expression variable in regard to the parameter...
Hi Andrew, Your solution worked perfectly! Now it takes the corresponding BW_ideal variable at each control_bit value. The paramset stuff I used earlier for the transisent simulation and was working...
View ArticleForum Post: RE: .lib files generation for custom analog design
DCM has been de-emphasised and is not in the menus any more (it used to be launched from the CIW Tools menu, but that was removed in IC616). The right way to generate .LIB files for a mixed signal...
View ArticleForum Post: RE: vr_ad and AXI eVC integration
The code piece for i from 0 to size { result.add(0x0); }; seems to be wrong/superfluous. At least in my case, it made the read_reg macro return twice the expected data (with zeroes in the extra bytes),...
View ArticleForum Post: RE: Changes to Tcl in 17.2
The major change was to 64-bit and this, potentially affects any binary libraries that were used by the script. If you wrote the script, you will be aware of any binary libraries that were used and...
View ArticleForum Post: RE: .lib files generation for custom analog design
Thanks Andrew, Can normal Liberate tool be used for analog ? Is the the AMS version more suitable from functionality perspective or from accuracy perspective ? Is the AMS version understand the...
View ArticleForum Post: RE: SKILL: Need to detect Duplicate Coincident Instances in...
I think I understand what you want. I dont know of a function or an easy why of comparing overlaps or overlays. Maybe to keep the data from grow too big, you might want to divide the top level in...
View ArticleForum Post: RE: .cdsplotinit setting for plotting on 11*17
Hi Quek, The link to that article is dead so I cannot view it, ut I am having the same issue. Here is my .cdsplotinit: Secure_Print|Canon iR-ADV C5250/5255 PPD: \ :manufacturer=Canon: \...
View ArticleForum Post: RE: .cdsplotinit setting for plotting on 11*17
Hi Miguel As this thread has already ended in May 2014, would you please kindly start a new thread for your issue? This will help us to focus on your issue and not be distracted by the other old...
View ArticleForum Post: .cdsplotinit and trying to print schematics on 11x17 paper
Hi, We recently installed new printers which have the option of printing to standard Letter size (Drawer 1) or 11x17 (drawer 2). I added the printer to my .cdsplotinit file however, every time I select...
View ArticleForum Post: vbit source in analogLib
I tried using the vbit source from analogLib in cadence virtuoso 5.1.0 04/26/2009. I would like to simulate my design with a specific bit pattern. but it gives me error. please see attached snapshot...
View ArticleForum Post: Translate ConceptHDL to Orcad
Hi experts, Is there a method to translate ConceptHDL schematic to Orcad schematic? If not, can you tell me how to translate ConceptHDL library to Orcad library? Thanks Chris
View ArticleForum Post: Basics about wire labels and general text
hi 1) Can a wire be defined with two wire names with some dummy element between them. (actually during my simulation tests i have to bypass the switch to check the o/p therefore one name either at...
View ArticleForum Post: RE: vbit source in analogLib
My guess is that you're using spectreS rather than spectre as the simulator interface. That has been obsolete since IC443 when the new "spectre" interface was introduced. Given that IC443 came out...
View ArticleForum Post: RE: Basics about wire labels and general text
Answers: It's not entirely clear what your objective is here - what is the purpose of this "dummy element"? Why do you need two names? It sort of sounds as if you want to use basic/cds_thru/symbol...
View ArticleForum Post: RE: .lib files generation for custom analog design
Generating a timing model for "analog" doesn't exactly make much sense, so the point here is to have something where you can identify the timing arcs and then have it pull out the relevant paths to...
View ArticleForum Post: Data conversion between Python scipy and numpy and SKILL
Hello all, I'm new programmer of SKILL and wanted to ask if it is possible to stream data between scipy and numpy library operations from python (like vector and Matrix operations ) and SKILL codes and...
View ArticleForum Post: RE: Verilog A code with lookup table
I don't believe so currently. I think the requirement for isolines should be relaxed if you are using "D" mode, in addition to it being changed to give the closest fit rather than an exact match only....
View ArticleForum Post: Invoke Callbacks in Pcell and PVS
Hello, I am building a PCell which includes a transistor of a PDK and to invoke the callbacks I am using the CCSinvokedCallbacks function recommended in " How to call CDF callbacks procedurally from...
View ArticleForum Post: RE: Basics about wire labels and general text
actually i made a transmission line schematic. I am looking at input and output. For some testing purpose; i have to eliminate the inductor in between two lines; in that case the input and output...
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