Forum Post: import spice model to one of the commercial OTA ICS
I've been able to import models using this guide , unfortunately, it doesn't work. The cell view is called OTA and the model file and subcircuit is called LT1228 In particular, I'm trying to import...
View ArticleForum Post: OrCad Capture 16.3: "No signals Present"
When I was trying to edit an older design which my senior had done. When I right click on any Netname, Aliases or Offpage connectors and selecting ' signals ' to see where it is routed it was throwing...
View ArticleForum Post: cannot pass uvm_sequence_item to send_to_dut
Hi all, Problem: I cannot call within uvm_driver the method send_to_dut with uvm_sequence_item. send_to_dut without argument can access class items of uvm_sequence_item , though. My example is based on...
View ArticleForum Post: RE: ahdlLib opamp model vref pin
It's effectively an internal common-mode node; it doesn't have much (if any - I didn't exhaustively check it through) influence on the output (it might if the ibias is large enough, or you're slew rate...
View ArticleForum Post: RE: import spice model to one of the commercial OTA ICS
Hi Nahla, First of all, I removed the model file from your post because it was copyrighted material and so should not be published on our web site. Secondly, this would be easier because I think this...
View ArticleForum Post: RE: ahdlLib opamp model vref pin
Thank you. Actually I checked the code line by line and if I understood it correctly it is a common mode voltage for the output. However, it is strange that output common mode voltage doesn't change...
View ArticleForum Post: RE: ahdlLib opamp model vref pin
[quote userid="354815" url="~/cadence_technology_forums/f/custom-ic-design/37202/ahdllib-opamp-model-vref-pin/1355641#1355641"]However, it is strange that output common mode voltage doesn't change when...
View ArticleForum Post: RE: RotateSilkAssyRD.il does not "Center Assembly RDs at Part...
Try the attached. Without seeing your board I don't think I can help. community.cadence.com/.../8357.RotateSilkAssyRD.2.3.zip
View ArticleForum Post: How to add minimize & maximize button to a form using skill
Hi , How to add minimize & maximize button to a form using skill? By default , it has only close button. Thank You.
View ArticleForum Post: RE: Free Gerber AND Drill-data viewer?
I have not downloaded a possibly newer version of the Pentalogix Viewmate for some years. The free version that I am using has the .ZIP-file import menu choise grayed out, so I cannot test this. From...
View ArticleForum Post: Balance Clock Tree Skew and levels of two different Block...
Hello everyone, I have two blocks separately implemented using the Encounter. They have huge CTS Global skew and i am unable to balance the CTS of two blocks and having hold violations between the very...
View ArticleForum Post: RE: How to add minimize & maximize button to a form using skill
You can't. The minimize/maximize buttons are something that is under the control of the window manager and not something an application programmatically controls. For some window managers (such as...
View ArticleForum Post: RE: Create Functional Verilog from Schematic.
Thank you for your answer tpylant! Since I couldn't find any info from a search I did about the RAKs, are they free or is this a paid service?
View ArticleForum Post: RE: Create Functional Verilog from Schematic.
The RAKs are free for Cadence customers, so if you have a login on Cadence Support, then you can download them and use them.
View ArticleForum Post: RE: Create Functional Verilog from Schematic.
Thank you for your answers! I will definitely then, download and go through them!
View ArticleForum Post: RE: Create Functional Verilog from Schematic.
A side question relative with my subject: I managed to overcome the above errors by adding the parameter " functional " in the " Stop Netlisting at Views " option of the " Netlist Setup ". I tried the...
View ArticleForum Post: RE: How to add minimize & maximize button to a form using skill
Thanks Andrew, for your inputs. I will try it & get back. Regards.
View ArticleForum Post: RE: Create Functional Verilog from Schematic.
The best thing I managed to do for the moment is to generate the complete netlist in a single file. Again this is not compiled straightforward way using NCVLOG , as some of the sub-cells are using the...
View ArticleForum Post: RE: Running a SKILL script from Command Line
Hello Andrew, Thanks for the clarification. Is there a db* alternative for schCheck( myCellView ) , for schematic checks? Best regards, Karam
View ArticleForum Post: Convert Digital Bus to an Integer value - Calculator Viva
I would like to check the integer output of a decoder matches the integer value i set using the busset instance that drives the decoder. ive tried using awvDigital2Analog() and numConv() but just cant...
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