Forum Post: change RefDes in schematic causes changes in pcb routing
Good day every one! i use Allegro CIS & PCB 16.6 I have complex hierarchical design divided into several pages. Each pages included couple of several logically separate circuits. I want to move...
View ArticleForum Post: RE: Silk to Solder check in Allegro PCB
try electronic.ui3g.com you may find lot of things about pcb
View ArticleForum Post: RE: change RefDes in schematic causes changes in pcb routing
I would uncheck the "allow etch removal". This may help or not. If it's just a simple change (like above) you may be OK. If not then once the netlist has been imported, use Place - Swap - Components...
View ArticleForum Post: RE: change RefDes in schematic causes changes in pcb routing
function "allow etch removal" only give old etches to stayed at board, this is not solution - parts are not moving -> routing broken. Swapping R3 -> R4 it is only simple example. The main goal is...
View ArticleForum Post: Synthesis with multi-thread CPU
Hi, Please help me with the problem below. I am doing with RTL Compiler now and when I run the synthesis of my circuit, it really takes a lot of time. Our server is separated into some virtual machines...
View ArticleForum Post: RE: change RefDes in schematic causes changes in pcb routing
You didn't mention whether, or not, you had run Back Annotation to synchronize the board and schematic before making any schematic changes...
View ArticleForum Post: RE: After Doing Silkscreen, Not getting Component Name ,...
What settings have you got for the Artwork Film that you are trying to output? The Silkscreen process will only generate the Autosilk layer(s) data, you need a Film defined in Artwork to output this to...
View ArticleForum Post: RE: change RefDes in schematic causes changes in pcb routing
Schematic and board are synchronized.
View ArticleForum Post: RE: Synthesis with multi-thread CPU
Hi Minh, yes! multi-threading will help but there are many aspects that impact runtime. Without any details about your design, your current runtime, etc. it is unlikely for community members to be able...
View ArticleForum Post: RE: change RefDes in schematic causes changes in pcb routing
Here's a little trick I do sometimes (Allegro): 1. Before I read in the logic (netlist) I copy the component in allegro outside the board area. 2. I swap the two undefined ref des components with the...
View ArticleForum Post: RE: Voltus power --- How to do vector based static power...
i think you have to run voltus 10 times, each time with a different start/stop time.
View ArticleForum Post: Is there a way to plot BSIM model parameters in Cadence?
I am wondering if there is a way to plot BSIM model parameters in Cadence or not. Some parameter like Early voltage VACLM which is not included in DC operating point. I know that we can exactract it...
View ArticleForum Post: How to create "extracted netlist file"
Hi All I am trying to update the binding in the layout view with LVS results, in order to make the view Layout-XL compliant. When reading the Cadence document, 2 files (.ixf and .net files) are needed...
View ArticleForum Post: skill code equiv of ADE-XL Create/Spec Summary and Plot all...
I have a family of IP (amplifiers for the sake of discussion) and I'm moving away from ADE-XL to Ocean-XL for simulation. Why? Because I have a variety of different designs which are pin compatible but...
View ArticleForum Post: RE: How to preserve the internal signal name in synthesis when...
Hmm.... "Topic has 0 replies and 6091 views." Seems like there are a number of folks also having the same issue, yet "0" replies. You would think this might have made the R&D priority list. And...
View ArticleForum Post: RE: How to preserve the internal signal name in synthesis when...
R&D does not monitor this forum. If a user has a serious issue, they need to contact support. This is a user forum, for users to help each other out with design issues and tool usage. Cadence...
View ArticleForum Post: RE: How to preserve the internal signal name in synthesis when...
Hi Jeff, as Kari pointed out, this is not a replacement for your support contact but a means for the community of ALL tool users to help each other out and share knowledge. You can be mad at the 6091...
View ArticleForum Post: multiple cells - single layout
Hi, I have 3 cells with each their own lib-model. Since the layout of the combination of these 3 cells is very critical, I would like to use a single layout for the combination of these cells. So in my...
View ArticleForum Post: Default Properties For New Schematic Symbols
Is there a way in Capture CIS to set default properties for new schematic symbols? For example when I create a new part I want it to include the following properties with blank values: - Manufacturer -...
View ArticleForum Post: RE: Default Properties For New Schematic Symbols
This is not a requirement for Capture CIS, unless you want to display those properties, which would be unlikely, Capture CIS will automatically add any properties set to Transfer to Design in the CIS...
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