Forum Post: RE: PSpice to Spectre "translator"
Hi, there are various documents on support.cadence.com which could be of interest for you: Here , here and here . Kind regards, Matthias
View ArticleForum Post: RE: Is there any command to extract a Veriloga in SKILL
Hi Andrew, Every time we modify the veriloga file, we try to save and extract so that the pin information is gernerated. So I am looking for a way in skill to save and extract a verilog file or...
View ArticleForum Post: RE: Standard cell Import issue (spice to schematic) using Spice...
HI Quek, Thanks for your reply, It works by modifying the Device map file to w w l l and actifivating the CDF callback switch in the Spice In option. Best Regards KC
View ArticleForum Post: RE: Send dc match results to the outputs
Lewis, It's not clear to me what you'd want. Normally the point of dcmatch is to see all the contributions to the mismatch, and so it's not obvious what you'd want to appear in the ADE L outputs. We...
View ArticleForum Post: RE: Where do I modify sheet resistance values for layout when...
This isn't something we can safely discuss in a public forum without the danger of breaking the foundry's NDA. It would be better to talk to the foundry, or customer support at least rather than doing...
View ArticleForum Post: RE: Mirroring in Bottom of Bottom
Do't use angle axlTransformObject(mirror_objs, ?mirror 'GEOMETRY)
View ArticleForum Post: RE: SKILL code to determine if two points are connected in layout
Writing a complete net tracer in SKILL is quite a lot of work - I know others on the forums have done so themselves, but if I was you I'd re-use the mark net capability. What I'd probably do is: Use...
View ArticleForum Post: RE: Reading an input file using std.textio
Sorry, I should have posted more of the code. I'm using basically this: process FILE vector_file_in: text IS "test_in.txt"; VARIABLE input_line : line; VARIABLE str_stimulus_in: string(8 DOWNTO 1);...
View ArticleForum Post: RE: SKILL code to determine if two points are connected in layout
Thanks Andrew! This is very clear.
View ArticleForum Post: RE: Efficient way to create vpi handles and callbacks
Hi Stephen, Thanks for your response. In a Netlist simulation we are trying to keep track of multiple (which I need to create callbacks for) wire/nets in my design and on basis of some rules I...
View ArticleForum Post: RE: captab simulation problem
Hello Andrew ,I have attached my Cadence virtuoso version,and how i defined my captabs i dont get any time variyng option in the table. Thanks
View ArticleForum Post: How to add a new additional pin in a already existing symbol in...
Hi, I have tried to add a new additional pin in a already existing symbol in allegro part developer. But when I give map I'm getting the following error, Please help to resolve this.
View ArticleForum Post: RE: captab simulation problem
[quote userid="4936" url="~/cadence_technology_forums/f/rf-design/41935/captab-simulation-problem/1361339#1361339"]Instead of this, just enter the times in the infotimes field, and then on the Misc...
View ArticleForum Post: RE: PVS rule file syntax check
Thanks Steve for moving this into the right forum. If you run: pvs -drc -get_rules rules.txt YourRuleFile.rul > pvs.log Then this will just run the check on the rule file without running a DRC or...
View ArticleForum Post: RE: Intercept custom skill function before execution
Hi Alistair, There is a trigger which can be registered when the current window changes: procedure(CCFcurrentWindowChanged(winNum) let((winId cv) unless(winNum==0 winId=window(winNum) ) when(winId...
View ArticleForum Post: RE: help - skill code for goto xy coordinate
Karthik, Given this code was written 9 years ago and I can't see other posts by Satya (at least not recently), I suspect you won't get an answer. Not sure I have the time to take the code, reformat it...
View ArticleForum Post: RE: AMS simulation with digital simulator on top
This is covered in Introduction to AMS Designer Simulation Andrew
View ArticleForum Post: RE: Is there any command to extract a Veriloga in SKILL
In general you should edit it through the editor in Virtuoso which will then do this, but you could just call: vmsUpdateCellViews(?lib "mylib" ?cell "amplifier" ?view "veriloga") Andrew.
View ArticleForum Post: PVS (SilTerra 130nm) not appearing in Cadence.
I have installed PDK that support PVS (Silterra 130nm) in Cadence IC 5.1.41 but I don't have the PVS option appearing in the virtuoso layout editor. Can anyone please guide me? Thanking you in...
View ArticleForum Post: RE: Send dc match results to the outputs
Hi Andrew, Sorry for the lack of clarity. What I would like to appear is the estimated overall dc mismatch, which appears at the end of the summary after listing the contributions (3-sigma total...
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