Forum Post: RE: Viewing Classes in Simvision
As Tudor says, you need to probe the dynamic objects; this cannot be done from the $shm_probe system task, you need to use the Tcl commands. In general we don't recommend using the system tasks as they...
View ArticleForum Post: RE: Reading an input file using std.textio
The problem isn't anything to do with where your stimulus file is on disk, the error is coming from the parser, indicating something is wrong with your source code. I can't see anything obviously wrong...
View ArticleForum Post: RE: PVS rule file syntax check
Hi Suryansh, I've moved your question to the Custom IC design forum, as PVS fits into there better than the functional verification one (I know, it's not always obvious).
View ArticleForum Post: RE: Efficient way to create vpi handles and callbacks
As far as I'm aware there is no other way to do this, and frankly if you create millions of callbacks, your simulation performance is going to be really bad... What are you trying to achieve (at a high...
View ArticleForum Post: RE: Timing and scheduling actions in vManager
You would need to do the scheduling via another script / tool such as cron; vManager itself doesn't implement any scheduling as there are too many conflicting user requirements out there! vManager has...
View ArticleForum Post: RE: xmelab: *E,CUVDNF (./netlist.vams,1748|8): Could not...
Really not enough information to help you here, if you cannot share more detail in public, please login to support.cadence.com and file a ticket so one of the hotline team can assist in private.
View ArticleForum Post: RE: Reading an input file using std.textio
The syntax for declaring an input file changed between the '87 and '93 versions of VHDL. If you are using -v93 or -v200x you can declare your file like: file input_file: text is "test_in.txt";
View ArticleForum Post: RE: Incorrect netlist of a circuit containing multibit instances...
Take a look at https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nXRwEAM . However, trying to find the root cause of the problem as Andrew suggested is probably still a good idea.
View ArticleForum Post: RE: Setup text editor for Library Manager
You have to set the useExternalEditor variable. Take a look at https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000u9GSEAY .
View ArticleForum Post: RE: Export physical error
Hi Mike, I got the folder and added the above information in that. Thanks.
View ArticleForum Post: RE: Incorrect netlist of a circuit containing multibit instances...
Thanks Frank. That workaround is not something we'd want to encourage except in the case of working around a short-term bug, as it leads to a loss in performance by disabling the incremental...
View ArticleForum Post: Installation procedure of cadence virtuoso + MMSIM + assura on...
can you please give me a well described setup guide for cadence IC 06.17.700 virtuoso + MMSIM 15.10.257 + assura 615 on centos
View ArticleForum Post: RE: Setup text editor for Library Manager
Adding the following line editor "editor_name" in the .cdsinit settles the case
View ArticleForum Post: Send dc match results to the outputs
IC6.1.7-64b.500.13 Hi all, I wonder if there's a possibility of sending the results of a dc match simulation directly to the ADE-L outputs window. Typically, a summary of the dc match results can be...
View ArticleForum Post: RE: xmelab: *E,CUVDNF (./netlist.vams,1748|8): Could not...
What more information do you required StephenH. I have only removed hierarchy information. Other than that is the only information I am getting from xrun. Do you might know what is the intention of...
View ArticleForum Post: RE: Where do I modify sheet resistance values for layout when...
Thank you. I have a note from the foundry regarding the resistors I am implementing in my mixed-signal design. Some resistors have metal buses running over them and others are completely covered . It...
View ArticleForum Post: SKILL code to determine if two points are connected in layout
Hi, I'd like to figure out if there is a connection between two points in the layout. I know I can do that by "Connectivity->Mark Net": I define the via layers, click on one point and see if the...
View ArticleForum Post: PSpice to Spectre "translator"
Hi experts!!! I have this PSpice code (it's a PWM switch model extracted from Christophe P. Basso book - ISBN: 978-0-07-150859-9) but I don't know how to use it in a virtuoso (Spectre) simulation of a...
View ArticleForum Post: RE: xmelab: *E,CUVDNF (./netlist.vams,1748|8): Could not...
I've seen that message when I was connecting an analog signal to a digital port. In a mixed signal simulation, there are auxiliary files that I needed to add that described a "discipline" that...
View ArticleForum Post: RE: Send dc match results to the outputs
Dear Lewis, i don't know whether there is a direct way to add the result of a dcmatch analysis to the ADE-L outputs. You could try to open the simulation results in the ViVA Browser and search there...
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