if there is no plane on layer 1, you should get antenna vias. you can find antenna vias in the dangling line, via and antenna report. you can use this report for only the top or bottom layer not for the inner layers like layers 2 and 3. i always check the report as i do not want to have antenna vias in my design.
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Forum Post: RE: How to check copper to copper clearance?
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Forum Post: RE: How to check copper to copper clearance?
Because I use through vias, there will be a lot of antenna vias (that use for signals). I think your solution will be difficult to solve forgetting plane on inner layer.
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Forum Post: RE: How to check copper to copper clearance?
another idea would be to use a route keepout. the inner shape in blue in your layout should not be a dynamic shape but a static shape. then place a route keepout over the static shape and the route keepout area should be overlapped with the outer shape in red. you should set up the property of the route keepout with via allowed. since the static shape in blue is still in the keepout area, it should give you an error. you should waive the error so you have no valid error now. if you acciendally remove the static shape in blue, you should get a new error since the shape in red has a new shape within the keepout area.
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Forum Post: RE: Regarding available libraries for allegro_design_entry_HDl on internet
Eagle is one of the translators that only available in Windows installations.
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Forum Post: RE: Soldermask Check
hi why this code runs with below error these days E- *Error* fprintf: argument #1 should be an I/O port (type template = "ptg") - nil
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Forum Post: Export a Breakpoint
Hi all, I was running a simulation with Xcelium in Simvision and I save few breakpoints. I would like now to run another simulation (so from a different console) and loading one of the breakpoints of another simulation Is this possible? I try with the File -> Save Command Script and then sourcing the restore file but it is taking a lot of time
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Forum Post: Place bound overlapped by Route keep out.
Hai, I have to highlight when place bound Top and Bottom were overlapped by Route keep out if it possible can anyone guide me or share me the skill code please. I want to highlight and location report.
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Forum Post: Calibre xACT3D Extraction Speed Problem
Dear Sir/Madam, In PEX, we could speedup the processing time of extraction netlist by using "Multi-Threaded" or many of CPU to do. We found out the problem of placing the components in schematic. The speed of doing this is prolonged abnormally (a few hours for 100M size netlist). Previously, we did this quite fast but right now is slowing down. I am wonder that any method or setting to speedup the generation of schematics process. Thank you. Best Regards, Chi Fung
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Forum Post: Running multiple PAC simulations on the same PSS analysis
Dear All, I am trying to run PAC analysis for multiple i/p frequency values. Can it be done without running PSS multiple times if so, how it can be done. Kind Regards,
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Forum Post: Regarding Packages in Allegro PCB Librarian
I want to create a 32 pin qfn package using allegro pcb librarian but it has not shown any option regarding to in JEDEC Type , How to get a qfn package?
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Forum Post: RE: Difference in "Voltus_Power_Integrity_Fi_L" && "Virtuoso_Power_System_XL"
Hi Andrew, Is there any way to calculate the P2P resistance for multiple point. Quantus P2PR is doing great for a single point. However if i have 100 nets and i want to calculate resistance between them , its difficult to do it for every single net. I was trying to develop a script which will open the P2PR GUI ,auto click in the layout view and call the callback of "Calculate" button. But unfortunately this is not working. Can you please suggest if there is other way around ? Thanks & Regards, Amar
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Forum Post: RE: Calibre xACT3D Extraction Speed Problem
Chi Fung, Calibre is a product from Mentor (a Siemens Company) and not from Cadence. So you would be far better off asking this to Mentor customer support rather than the community forums related to Cadence tools. Kind Regards, Andrew
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Forum Post: RE: Running multiple PAC simulations on the same PSS analysis
If you are trying to find the transfer function from multiple different sidebands to a single expected output frequency (or sweep of output frequency), perhaps you would be better off using pxf instead of pac? pxf computes the transfer functions from each source in the design to the specified output, and can give you the transfer function from each sideband of the input frequency to the output. Otherwise the only way to do this is really to put the analysis statements in an include file and reference them via the setup->model libraries form. To do this I'd start with copying the pss and pac analyses from the input.scs for a single run into a file, then repeating the pac analysis with a different instance name (the first word on a line) and changing the input frequency. For example: pss pss fund=5G harms=3 errpreset=conservative tstab=10n + annotate=status pac pac sweeptype=absolute start=5.000001G stop=5.01G + maxsideband=5 annotate=status pac2 pac sweeptype=absolute start=4.000001G stop=4.01G + maxsideband=5 annotate=status pac3 pac sweeptype=absolute start=3.000001G stop=3.01G + maxsideband=5 annotate=status Then disable the pss and pac analyses from the choosing analyses form in ADE. You need to include the pss plus the N pac (rather than using a mix of the UI analyses and those from an include file) because there's an order dependency - the pac analyses need to follow the pss analysis in the netlist. Regards, Andrew.
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Forum Post: RE: Difference in "Voltus_Power_Integrity_Fi_L" && "Virtuoso_Power_System_XL"
Hi Amar, I don't think this is possible. You should contact customer support . Regards, Andrew.
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Forum Post: Which "efficient algorithm" uses ADE-XL for global optimization?
Hello, I am working on optimizing a design but the local optimization algorithms are not suffcient since possible solutions are not in the neighborhood of each other. That is why, I am using global optimization to get more diverse results in terms of the feature space. For better understanding this procedure it would be helpful to get some information about the used algorithm / optimization method. In the documentation, I did not find a more specific description as: (I cite the documentation) "It efficiently searches over all of the variables defined to find a good solution for your design". Could you please provide a short description or at least the name of the implemented optimzation procedure? I am looking forward to your answer. Thank you very much for your time in advance. Best regards
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Forum Post: RE: Regarding available libraries for allegro_design_entry_HDl on internet
Thank you so much sir. Ok i will try with windows installations also
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Forum Post: RE: Installscape/Cadence Installation Questions
With InstallScape you can either update an existing installation (which will delete the old parts of that installation and replace it with the latest hotfix). Or you can install in a fresh directory and then it will install the pieces it needs from the base release and hotfix release to build the entire installation. If you are doing the "Update" process in InstallScape (one of the installation modes) it would ask you where the current installation is. You do not have to point at an IC release to install INCISIVE (or the newer XCELIUM) or ASSURA releases. The order you install the releases in doesn't matter. In general I would suggest you just install the hotfix release directly as then it will only download the very few parts of the base release that haven't been hot fixed. This is assuming you use installscape directly rather than downloading the release images and then installing (again, you could just install the hotfix first) - doing so would mean that you download a lot of stuff that doesn't get used. If you use installscape itself to download and install releases it only downloads the components it needs, so that's more efficient in terms of the amount of data it needs to download. Regards, Andrew.
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Forum Post: RE: Use ".lib" timing file in AMS simulations using ADE
Not really my area of expertise (this requires the digital implementation tools), but you can do this in either Innovus or Tempus. You read the .lib for the cells, and the Verilog, and then use the write_sdf command to produce SDF. I'll move this into the Digital Implementation forum so that if you need more help you're more likely to get an answer. Regards, Andrew.
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Forum Post: RE: Which "efficient algorithm" uses ADE-XL for global optimization?
First of all, asking this question in the suggestions, questions and feedback forum is not a very good place to get an answer to a technical question. So I moved this into the Custom IC Design forum which is more sensible. Global Optimization is Cadence developed internal optimization algorithm which works well in nonlinear design space without needing a good starting design point. We don't reveal details of the algorithm because it is proprietary intellectual property. I don't really know why you would need to know the algorithm used to actually use the optimiser. Kind Regards, Andrew.
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Forum Post: RE: How to do back annotation for wire RC extraction from layout to schematic
We do not have a "wire RC model" and nor does any TSMC PDK. I don't know what you mean by "I have got RC parasitic readings from cadence". What is "cadence"? (there is no tool called "cadence"). How are you getting these "RC parasitic readings"? If you're using Quantus QRC to do the extraction, it would produce an RC network representing the parasitics on that track and coupling to other tracks. My wild guess is that you're using the visualisation capability that can display a single effective R and C value on the schematic - this is not intended to be used for simulation, but to give you a rough indication of the effective resistance of the net and the total capacitance. For anything other than a trivially simple connection that would give you a pretty inaccurate representation of the actual distributed RC network of the track. You would normally simulate using the actual extracted parasitics (e.g. by simulating with an extracted view), but there is support in the tools for selectively picking the parasitics from some nets and keeping the others from the schematic - so you keep your schematic golden but would then allow you to explore the impact of parasitics on specific rather than all nets. But it's unclear what tools you're using, what versions, or what you're actually doing here! Kind Regards, Andrew.
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