Hi Anuj, Please look at the following skill snippet for ideas: wr->OldName = instancepointer->name wr->NewName = pcreReplace( wr->pcre wr->OldName replaceValue 1) if( wr->OldName != wr->NewName then instancepointer->name = wr->NewName wr->Text = strcat( "set inst name: " wr->NewName) wr->Replaced = wr->Replaced + 1 ) You need to add a foreach loop to work on each of your instances. The pcre expression needs to be defined of course. In my case I use a wr->xx variables so I have only one local variable to define: let( ( wr) wr = ncons( nil) ... Regards, William
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Forum Post: RE: Renaming instances with a pattern in its name to a new pattern
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Forum Post: RE: Exporting ADE-L Design Variables into a CSV file
Strange, but now asiGetDesignVarList(asiGetCurrentSession( )) works... Now I only need to write the code to parse the list and export it to a CSV file.
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Forum Post: RE: Making a mathematical expression between two parameters in ADE GXL output setup window
Hi, I made indirect solution by taking abs(IM6-IM7) then I push this to ADE and select minimize to zero as a design target specification
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Forum Post: Running different type of simulation in one environment
Hello I would like to ask you how can I run a different type of simulation in one simulation environment, for example suppose I want to do the basic simulation of op-amp like -input common mode range -AC performance -transient performance -open loop response -etc I usually run every simulation individually in a separation schematic file, However, right now I am keen to use the circuit optimization from ADE GXL to optimize my design, if I run the optimizer for the AC performance then he might degrade the transient and so on, therefore I need to include all type of simulation to be checked by the optimizer so it can find the solution tha satisfy all the specifications am using ADE L, Spectre Simulator version 11.1.0.509 2012 and Cadence Virtuoso IC6.1.5-6b bit Thank you very much
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Forum Post: .dra to .dxf file
Hi I was wondering how can i export a footprint(.dra) file out to .dxf file. My dxf file comes out to be blank when i run export--> dxf and follow the usual procedure of naming output file and then edit--> select all--> use layer names--> map and then export
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Forum Post: Opening an ADE XL interactive test editor following an Ocean run
Hello, I usually run multiple simulations at the same time and use ocean script to do that. If I want to view the plots after, I view it in ADEXL environment. If I want to quickly run interactively after, I am neither able to edit the output setup nor able to view the test editor in ADE XL. 1) Could you please let me know why this is happening? 2) Is there an option to change the test editor from Ocean to ADEXL in an interactive run, following an ocean run? Thanks in advance, Krithika
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Forum Post: Saving terminal currents of extracted circuit breaks harmonic balance simulation
I have a CMOS inverter that I've extracted to a dspf file using Calibre xACT. When I save any of the terminal currents of the extracted block in a harmonic balance simulation, the circuit ceases to oscillate and the output is just a dc signal. Does anyone know why this happens? The simulation completes without error and it was just luck that I noticed this was the cause. I've tried it with transient and dc simulations but they run fine. I'm using Cadence ICADVM18.1-64b.83.
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Forum Post: Via-in-Pad on old Orcad Layout 16.2
Hi, I am still using Orcad Layout 16.2.0, and I need to use via-in-pad on the next PCB. I changed the pad attributes of a SMD 0805 resistor, checking the "Allow via under pad" setting in the footprint. But how I can put the vias under the pads of this footprint in the PCB? I only get errors like "Via will not fit". Thank you in advance M.
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Forum Post: RE: veriloga integer input to 32-bit address output has a strnage error/how to debug/where to find the latest veriloga reference documents?
Hi Andrew: Thanks for the support. The reason I am back is because the veriloga code failed for some other reason and I am not able to figure out how to properly load your skill code bussetp.il. I load it in CIW and it returns with the below error. =======start error report============= load("~/Downloads/bussetp.il") *Error* Couldn't open library "training" *Error* load: error while loading file - "~/Downloads/bussetp.il" at line 284 =========end of error report================== For the veriloga code, I have simplified my code to the code below but I still get error now, it works yesterday, weired. `include "constants.vams" `include "disciplines.vams" module integer2thermocodeOut(vdda,gnda,OutAddress); parameter integer BusWidth=32; parameter integer BusOn=8; input vdda, gnda; output [31:0] OutAddress; electrical [31:0] OutAddress; electrical vdda, gnda; genvar i; analog begin if (BusOn) begin for(i=0;i<BusOn;i=i+1) begin V(OutAddress[i]) <+ 1.0*V(vdda); end end end endmodule =======start error report============= Error found by spectre during hierarchy flattening. ERROR (SFE-100): "input.scs" 6403: `I101': An instance of `integer2thermocodeOut_BusOn_12' can have at most 0 terminals (but has 34). Clean up the directory and recompile or use command '-va,forcecompile' to recompile. If still fail, contact developer for help. ========end of error report========== I am using IC6.1.7-64b.500.23
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Forum Post: Unreadable background color (rectangle balloon information in Virtuoso windows): How to modify ?
Hi All, Usually, when hoving the mouse over a button, a menu or a blank space to fill, a rectangle information balloon popup to provide information about the function or what information is expected when filliing a form. I'm using 6.1.7, and in the current setting the background color is pink and the text is white so that the information are completely unreadable. (pic below) Does anyone knows where to modify this background color? Thank you Regards KC
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Forum Post: RE: Updating a PDK technology layermap and technology
Hi, I'm sorry to resurrect this thread after so long but in favor of other who might have similar issues: Apparently the techfile format has changed between IC6.1.4 and IC6.1.5. Found it in documentation. My solution around the update errors was to use IC6.1.4 to perform the update. IC6.1.4 still throws a bunch of warnings, but all of them appear in the CIW and are either streightforward to solve or go away once the techfile is dumped and reloaded. Thanks for the help!
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Forum Post: PVS-QRC vs Assura-QRC
Hi, I'm trying to migrate from Assura extraction to PVS. Tool versions: IC6.1.7 Assura41.6 PVS191 EXT191 I have LVS decks which were supplied by the fab (e.g. TSMC65nm GP), and both PVS and Assura LVS work fine (i.e. clean cell, no funny log errors). However, when running QRC with the Assura database it runs fine (again, no funny errors, result makes sense etc) but PVS-QRC terminates with the following error: "There was no library cell mapping file (extview.trp (V2) or icellmapfile.yaml), or alternatively the extview" What is happenning? I did some reading and it seems like the fab should give me either of the missing files. But then - how is Assura-QRC working? And if it does - Is there a way to retreive the missing information from the Assura deck files? I'm in contact with the fab but this might be lengthy. In the meantime any help will be much appreciated. Thanks! Matan
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Forum Post: HBnoise Error
I am trying to run a HBnoise simulation after a 2 tone HB Analysis.Here is the HB Analysis setup The HBNoise setup looks like the following My goal is to measure the Noise Figure(NF) by considering the Input noise in 400 MHz -401 MHz band folding back to the 1 Hz-1 MHz band at the output. However when I run the simulation,I get the following error message. I have tried selecting several different reference side-bands from the list and each option leads to the same error. I have also tried running a one tone HB analysis followed by a HBNoise simulation and I still get the same error. I would appreciate any help on getting this resolved. -Arnab
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Forum Post: RE: Via-in-Pad on old Orcad Layout 16.2
This seems to be working fine for me and I only get the "Via will not fit" for conflicts with other routing. Quite likely getting the Vias into the pads may be the least of your concerns since OrCAD Layout has a limited number of Via Types and DRCs for "nested" Vias is limited, it also doesn't handle rules by regions and other things that are going help when working with Via in Pad and Blind / Buried Vias in "tight" designs. It may be possible that getting hold of another PCB tool, like PCB Editor, might make your efforts with this type of design more productive.
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Forum Post: RE: .dra to .dxf file
The devil may be in the detail of what you have in the symbol but following the "simple" steps gets me a DXF with the symbol data layered within it. I am using 17.2-2016.s060 so there is a small possibility that you have a different version / hotfix where this didn't work but I would be quite surprised if that was the case.
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Forum Post: RE: Via-in-Pad on old Orcad Layout 16.2
Hi oldmouldy, thank for your reply. It seems that now it works fine, after a "close-restart" of Layout. I will switch to PCB Editor in the future, but since it has a lot of differences from Layout, I need some time to learn it. Thank you again.
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Forum Post: RE: RMS and AVERAGE Calculation with respect to power.
Hi, I am interested to know how spectre calculates the dc(avg), peak and rms currents , and how the average current can be negative ? I have just used the keyword "rms" and " em_avg" in the .meas statement. Please provide some insights on this. Thanks,
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Forum Post: Get simulation state name of an ADE-L session
Dear all, I would like to get the simulation state's name of a loaded session in ADE-L using SKILL. There are functions like asiGetDesignLibName(), asiGetDesignCellName() and asiGetDesignViewName(), delivering, for example "ahdlLib", "testbench_opamp" and "schematic", respectoively. Yet there does not seem to be a function returning the name of the saved ADE state that has been (re-)loaded into ADE-L, like "spectre_state1". What I can find is a generic name (e.g. "spectre6"), like o_session = asiGetCurrentSession( ) o_session~>name , but not that of the user-defined state name. Is there any way to determine this name in an easy manner? Thank you.
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Forum Post: Does hbnoise support the ideal switch from analogLib?
I am running the circuit below and get the phase noise using pss/pnoise as well as hb/hbnoise. It is a frequency divider(divide-by-two) in which I used sample-and-hold circuits instead of latches to keep it "analog". pss/pnoise gives expected results whereas hb/hbnoise shows zero phase noise at the divided outputs ckI and ckQ. Is the switch not supported by hbnoise or could there be another problem? The log shows the following warning. The frequency in the warning is always the last point I specify for hbnoise. Warning from spectre at freq = 10 MHz during HBNOISE analysis `hbnoise'. WARNING (SPECTRE-16518): Arithmetic exception in analysis `hbnoise' . Schematic snapshot and netlist attached. Virtuoso IC6.1.7-64b.500.3 Spectre Version 17.1.0.307.isr6 64bit -- 4 Jul 2018 Nagendra
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Forum Post: RE: Does hbnoise support the ideal switch from analogLib?
Somehow the netlist isn't getting attached. It is at https://drive.google.com/file/d/1zfNfs2q9zO5wT3-pGWHjGT9QkP39nOBO/view?usp=sharing Nagendra
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