In our team we make a hierarchical copy of our individual blocks for the final library in a tapeout. I'm using some pcells that rely on code in the libInit files. However, the hierarchical copy copies only the cell, obviously not the needed code in the libInit file. Is there a way to automatically flatten (or something else) these pcells to have a truly standalone library (without other team members needing access to the original pcell library with the respective libInit files)? This is not necessarily a question about SKILL, if there is something implemented in virtuoso I'm happy to use that. Kind regards, Patrick
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Forum Post: Freezing Pcells for tapeout with external code in libInit.il files
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Forum Post: Technology independent layout library
I work in a small team where we don't all use the same technology, but we have on major most-popular technology. Now I've started to build some pcells to make my work easier, and I'm sharing them with the team. For this one technology this is fine, but since the cells started becoming more and more useful, I've thought about expanding them to different technologies. Now I now that we can get a list of layers from the tech file, filter for metals (for example) and build pcells automatically with this information. However, (if I understand correctly) the technology library has to be selected. What happens if the cell is instantiated with the wrong technology selected? Is it possible that the technology is automatically taken from the library where the pcell is instantiated? Furthermore, a major concern is the dealing with NDAs. Not everyone in the team has signed up for every technology, so everyone should only have access to the technology they are allowed (so I can't have a file storing all the layer information, even if it's just layer names. I guess that already violates certain NDAs). In the end I want to have one library that fits 'em all, if possible. Now I'm definitely not asking for a solution here, but maybe someone can give me some pointers how to start something like this. Kind regards, Patrick
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Forum Post: RE: HBnoise Error
Adding the tool information Spectre (R) Circuit Simulator Version 17.1.0.160.isr2 64bit -- 26 Jan 2018 Virtuoso IC 6.1.7
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Forum Post: Generate verilog cellview for use in AMS from schematic of standard cell
Is it possible to generate a verilog or other cellview for use in AMS from a schematic constructed from standard cells (TSMC cells, in this case)? I want to improve mixed-mode simulation time by extracting a digital representation of this portion of the circuit. Apologies if this is a dumb question; I'm a bit of a novice. This seems like this should be straight-forward, if somewhat in reverse of the typical use, but I've spent hours going through documentation had trouble getting traction on this particular use-case. If anyone can point me in the right direction, it would be appreciated.
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Forum Post: Unbound pins when running Assura LVS in Virtuoso Layout
hello sir, when i draw the layout of the buffer circuit, there is no DRC error but there is one LVS error that occurred which is related to unbound pin.i attached the image of my layout, in this image the highlighted part shows the error.
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Forum Post: RE: Unbound pins when running Assura LVS in Virtuoso Layout
In my schematic, there are only 4 pins. In LVS an error occurred between the drain of the first inverter to the gate of the second inverter which shows unbound pin error, how I can resolve this issue please suggest some options.
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Forum Post: Virtuoso Layout Migrate FLOW works successfully, but the migration result is wrong
Dear all： I transfer layout from tsmc18 to smic18 with VLM tools. As shown in the figure below, the VLM flow indicates that migration works successfully. and I checked my setups, there seems to be no problem with the settings as shown in the following figures. but the instances in transformed layout view is not at correct place. Is there a problem with my setup and how to solve it ? thx for your reply
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Forum Post: RE: Wanted to learn Skill coding
Hi Eugene, Thank you for your help. I will start with this. Leelaprasad
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Forum Post: *Error* putprop: first arg must be either symbol, list, defstruct or user type - nil
Hello, When I try to instantiate a transistor, I get the following error: *Error* putprop: first arg must be either symbol, list, defstruct or user type - nil *WARNING* (SCH-1156): CDF parameter function has a problem. ("nmos4") My virtuoso version is:sub-version IC6.1.8-64b.500.1 I looked up the forum and there was similar issue years back as posted here: https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/22865/launch-lehicreateinst-it-shows-error-putprop-first-arg-must-be-either-symbol-list-defstruct-or-type-nil I tried the suggested methods but no luck. Thank you so much.
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Forum Post: DRC: shape to route keepout spacing
I have fiducial marks on my board and i am getting error under unassigned shapes/drc as shape to route keepout error. There is no route close to this fiducial. The orange line is my route keepin boundary. When i move this boundary such that fiducials are outside this boundary, then i am getting additional errors as shape to route keepin. How to get rid of these?
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Forum Post: RE: DRC: shape to route keepout spacing
HI, your fiducial should be built with a "route Keep out", on all layers. not "route keep in". This should fix your problem., i hope this works for you. Cheers
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Forum Post: Pad Editor: Difference Between Mechanical Hole, Tooling Hole, and Mounting Hole.
I am wanting to make some non plated through holes for mounting a PCB into an enclosure. I only see people giving advice about using basically the mechanical hole but set it to non-plated. That is fine to do but what is the difference between the pad types mentioned in the title? I would imagine that the mounting hole should be used but is there a significant difference? I am a user of version 17.2.
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Forum Post: How to reuse circuit INITIAL conditions (at simulation time t=0) at multiple instants during a single transient run
Dear All, I want to inject a pulse current at certain node of a periodic circuit like Oscillator. I need to check the oscillator's steady state phase shift if the pulse injection happens at different instants during one period of oscillation. This can be done, by running multiple simulations ( basically a parametric sweep) with shifted instants of pulse injection. But, running multiple simulations is very time consuming. To speed up the simulation process, one can run the simulation at one go with reusing circuit INITIAL conditions (at simulation time t=0) at multiple instants. For example:- If total duration is 1000 ns, I can reuse the INITIAL condition at 200ns, 400ns, 600ns ... ... 800ns, The pulse injection can happen at 150ns, 460ns,670ns ..... 890ns (shift of 10nS from the previous instant). Can anybody please tell how this can be achieved ? Kind Regards,
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Forum Post: Noise Analysis for Modulated Noise Using Verilog-A Modelling
Hi Community, I am doing experiments about modulated flicker noise and I aim to stick to Verilog-A behavioural modelling. Below is the test bench I brought up and the Verilog-A modules that I wrote seperately: // VerilogA for lab_simu, noise_source, veriloga `include "constants.vams" `include "disciplines.vams" module noise_source (op); output op; voltage op; analog begin V(op) <+ flicker_noise (1000,1,"Flicker") ; end endmodule // VerilogA for lab_simu, Oscillator_fixed_freq, veriloga `include "constants.vams" `include "disciplines.vams" module Oscillator_fixed_freq (out); output out; voltage out; // output signal parameter real freq = 1e9 from (0:inf); // output frequency parameter real vl= 0; // high output voltage parameter real vh=1; // low output voltage parameter real tt=0.01/ (1e9) from (0:inf); // transition time of output integer n; real next; analog begin @(initial_step) begin next = 0.5/freq + $abstime; end @(timer(next)) begin n = !n; next = next + 0.5/freq; end V(out) <+ transition(n ? vh : vl, 0, tt); end endmodule // VerilogA for lab_simu, mixer, veriloga `include "constants.vams" `include "disciplines.vams" module mixer (vin1, vin2, vout); input vin1, vin2; output vout; voltage vin1, vin2, vout; parameter real gain = 1; analog V(vout) <+ gain * V(vin1)*V(vin2); endmodule Nothing terribly bizarre. The question is, I would love to extract the Noise Power Spectral Density measured in V^2/Hz for both 'noise' and 'output': when I set the noise analysis as below: I get the plot expected (green curve is noise PSD and red line is that taken 10dB - a straight line!): However, when I set the 'positive output node' in the noise analysis to be the modulated noise output, I got nothing in the plot (0V^2/Hz for the whole spectrum): Could somebody explain why and suggest any solution to it? I want to plot the noise PSD of the output modulated noise. In case noise analysis could not handle this task. Could somebody suggest in which analysis I can extract the same nice noise PSD plot as in the first case and how? Thank you so much!!!
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Forum Post: RE: How to disable/enable a device in schematic pcell while netlisting
Hi Andrew, Thank you so much for the Example script to create a schematic Pcell. It really helped me to create a PCELL for capacitors Regards, Prasad
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Forum Post: Skill solution for smartSnap in layout
Hi, Most of the layout functions have now got a smartSnap option. For example: for "leHiCreateRect()", we have the following to turn the smartSnap on/off leRectXLForm->rectSmartSnapEnable->value= t leRectXLForm->rectSmartSnapEnable->value= nil for "leHiCreateRuler", we have the following to turn the snap option on/off ruler->rulerSnapOff->checked=t ruler->rulerSnapEdges->checked=t So, i was thinking if i could set a global bindkey to turn the smartSnap on/off for all such functions. What i mean is, when the "leHiCreateRect()" is active pressing the bindkey for example "Shift s" would toggle the smartSnap for it on/off and if the function "leHiCreateRuler" is active, the same bindkey "Shift s" would toggle the smartSnap on/off for it. Can anyone help out with a SKILL solution? I think its a good to have feature built in Cadence tool itself. Thanks Ram
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Forum Post: RE: Combining Different board files
You might have got a reply if you'd posted this in the right place. The forum you posted in was "Feedback, Questions and Suggestions" which is for issues with the forums themselves, not for technical questions. I'll move this into the PCB Design forum which is the right place. Also, for anything urgent, you should contact customer support (support.cadence.com) rather than expecting a response from the community...
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Forum Post: RE: Are there any specific gotchas for using OCEAN with SKILL++?
No gotchas that I'm aware of. Should be fine - much of the underlying ADE and OCEAN code is actually written using SKILL++ anyway! Andrew.
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Forum Post: RE: Interface port coercion
Hi Mario, I have also based a uvm verification environment on the papers you have referred to. I have a gpio interface with ports being declared as input and the code simulates fine with VCS. However, the agent was not able to drive a signal into the dut which led me to believe that ports were not coerced. I added the -rnm_tech switch of xrun and it did it for me. I am running with xcellium 19.03.013. Regards, Omid.
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Forum Post: RE: Unreadable background color (rectangle balloon information in Virtuoso windows): How to modify ?
Check out this article: Plasma desktop on KDE: Tooltips in virtuoso unreadable with system default setting of white Tooltip Text (there's also another linked article at the bottom of that which may help). Andrew
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