Normally you only get a text editor in ADE XL for the test if you ran a simulation using an OCEAN XL script, and then opened the view with ADE XL and then used "Load Setup to Active" rather than "View Results" over the OCEAN history that was saved. If you do that, then you can no longer use the ADE XL test editor because you've just set the active setup to be the OCEAN script. You can use Load Setup to Active over an older history which was run interactively in ADE XL, or if you had saved a "setup state" then you could re-load that. However, I'm guessing a bit here because I don't know precisely what you've done... Regards, Andrew.
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Forum Post: RE: Opening an ADE XL interactive test editor following an Ocean run
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Forum Post: RE: Exporting ADE-L Design Variables into a CSV file
ADE Explorer already has this (right mouse button over the Design Variables in the Setup Assistant), as does ADE Assembler (right mouse button over the Global Variables in the Data View Assistant). There are entries to Export and Import to/from CSV. For ADE L you'd need to write your own. The likely reason it didn't work before was probably that the current window wasn't correct, and asiGetCurrentSession() wasn't returning the current session because it didn't know which session you were talking about. ADE L is in "Sunset mode" so you really should migrate to ADE Explorer if you can. Regards, Andrew.
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Forum Post: RE: Ocean parametric sweep fail due to memory
I'm not sure why the memory should grow - you should contact customer support about that. I was thinking that you could just use: envSetVal("spectre.envOpts" "controlMode" 'string "batch") at the beginning of your OCEAN script, but with paramset it still runs a s a single invocation of spectre (conventional parametric analysis would invoke spectre separately for each run). You could use ADE XL or ADE Assembler instead. You define the individual variables as a list of the values you wish you sweep, and then select the variables in the list of global variables and use Right Mouse->Group as Parametric Set. If you do it this way, each simulation will be an individual run and so the memory should not accumulate. Regards, Andrew.
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Forum Post: RE: How to save wave as text information rather than wave plot
The intersects function returns all the crossing points. If you want to have an ADE output which is just the first (say), then you could define three expressions: Name Expression allIntersects intersect(VT("/vin") VT("/out")) firstX firstVal(allIntersects) firstY value(allIntersects firstVal(allIntersects)) Of course, the first is whatever you want. If you select the first not to plot, but the second two to plot, then it will show the numbers in the ADE L outputs pane. Regards, Andrew.
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Forum Post: RE: *Error* putprop: first arg must be either symbol, list, defstruct or user type - nil
Can you try doing: tracelength=tracelevel=_stacktrace=50 and then using the schematic editor create instance command (the other post was about layout, so isn't directly applicable). This seems to be a bug in one of the CDF callbacks of the component you're instantiating, so it's very likely to be specific to the PDK or component you're using, rather than a Virtuoso bug. I'm hopeful that the above might give more of a clue as to which callback function is failing. If that doesn't help, you might also need to do: sstatus(errsetTrace t) and try again. Please post the CDS.log file entries you see having done this... Regards, Andrew.
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Forum Post: RE: Virtuoso Layout Migrate FLOW works successfully, but the migration result is wrong
Please contact customer support . We'd need to see your VLM setup to understand this. Andrew.
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Forum Post: RE: Generate verilog cellview for use in AMS from schematic of standard cell
If you have a schematic containing instances of standard cells, then the Verilog-AMS netlist produced already is a Verilog netlist of the gates. The question is whether you have verilog models of the standard cells, or whether it is net listing the schematics of those standard cells and hence simulating down to transistor level. So, are there any verilog textual views of the standard cells in your library? If so, what are the views called? If not, what view names are available? Do you have a text file somewhere outside of Virtuoso containing Verilog descriptions of these standard cells? Regards, Andrew.
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Forum Post: RE: Get simulation state name of an ADE-L session
The trouble is that this is not something that is truly persistent (it's not a locked view, like it is with ADE XL/Explorer/Assembler), although ADE does remember it in the "sev" layer. So if you find the "sev" session of the ADE window: sevSess=sevSession(hiGetCurrentWindow()) sevSess->stateName will tell you the last loaded state name. Andrew.
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Forum Post: RE: RMS and AVERAGE Calculation with respect to power.
This has very little to do with the original question, which is one reason why the forum guidelines ask you not to post on the end of old threads. It also would have helped if you'd given the actual .measure statements you're using. Note that we primarily support .meas/.measure statements for compatibility with other SPICE simulators; the normal way to do this with Spectre would be to use Spectre MDL or ADE to compute the quantity. I'm assuming you have something like this simple spectre netlist: // I1 (n1 0) isource dc=1m type=sine freq=1M ampl=2m R1 (n1 0) resistor r=1k tran tran stop=2u simulator lang=spice **.option em_recovery=1k .meas tran av1 rms I(R1) .meas tran av2 avg I(R1) .meas tran min1 min I(R1) .meas tran max1 max I(R1) .meas tran av3 em_avg I(R1) em_rec=1 If I do that, I get: Measurement Name : tran Analysis Type : tran av1 = 0.00173168 av2 = -0.001 av3 = -0.001 max1 = 0.000997474 min1 = -0.00299432 In my results. The RMS is obviously always positive, but the avg isn't because it calculates the area under the curve in question divided by the interval (in this case the whole simulation since I didn't specify from and to in the .meas statements), and if you have more negative regions than positive the total area may end up being negative. In a definition of em_avg I found in a request for support for this .meas syntax, it says: Measure the average of positive part of the waveform (when I(t) > 0): "pos" Measure the average of negative part of the waveform: "neg". final em_avg current is: max(pos,neg) - EM_REC * min(pos,neg) the polarity of em_avg current is same as the polarity of the max(pos,neg), i.e. Positive, if abs(pos) is more than abs(neg) and otherwise. Regards, Andrew.
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Forum Post: RE: PVS-QRC vs Assura-QRC
Please contact customer support . We can't really provide technology-specific advice in a public forum without breaking the NDA with the foundry, so you really need to do this via customer support.
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Forum Post: RE: veriloga integer input to 32-bit address output has a strnage error/how to debug/where to find the latest veriloga reference documents?
The busset code will need modifying to specify the library you wish to create the component in. From memory the code specifies it as a library called "training" but you can change the code to be whatever you want. That's why it's failing. Note however that you cannot create a bus wider than 31 bits though using this component because uses integer arithmetic and it's signed 32-bit integer. The VerilogA code should work OK - I suspect something has got messed up with your ADE simulation directory. You could try doing what it suggests - go to Setup->Environment and in the User Command line Option field enter: -va,forcecompile This will force the VerilogA to be recompiled. I'm not sure why it's failing without that (may depend on the Spectre version you're using though, which you didn't mention). Regards, Andrew.
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Forum Post: RE: Saving terminal currents of extracted circuit breaks harmonic balance simulation
No idea. Please contact customer support as I think we'll need to see the test case. Regards, Andrew.
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Forum Post: RE: How to reuse circuit INITIAL conditions (at simulation time t=0) at multiple instants during a single transient run
I don't think I understand why you would want to do this (you can't anyway). The initial conditions can only be used during the initial transient solution (the DC before the transient) and not re-applied part way through a transient (I have no idea why that would be useful, or why that would be any more advantageous than just running a separate transient simulation with each initial condition). Regards, Andrew.
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Forum Post: RE: Combining Different board files
Umm. I don't think you want to do that. If you get the same number of all three boards that pass final testing, you are extremely lucky. Keep each board separate to minimize pick-n-place setup time, and let them optimize things for that one board instead of chasing 100% yield with all three together. A board with 01005 parts may need a different paste stencil thickness to hit yield targets which will not work for another board having 0402 and larger parts. Similarly, the board with 01005 parts will need to be run on the latest generation of pick-n-place, which will be more expensive. But, a board with 0402 or larger could be run on cheaper machines. Your fabricator always uses CAM to panelize your data for their processes, materials, and equipment and check to make sure there won't be a high risk of shorts or opens or traces hit while the board outline is routed during final. Boards are always set up for photoplotting in CAM. You will not be able to bypass this. Some machines are able to load most of the different sizes of parts onto the same machine and not worry about conveyors set to a certain width (the size of refrigerators laid flat.) If Your assembly house has conveyors between multiple machines for high-volume, they should be the ones driving panelization optimized for their equipment. Pick-n-Place split between multiple machines to gain assembly speed absolutely requires Assembly panelization. This should also be optimized for board fabrication yield (you're paying to have a 12"x18" panel run through the fabrication process, it is to your advantage not to waste space on it.) Are you delivering reels of taped parts, "digi-reels" (custom quantity of parts on a reel from Digikey) This is critical for saving material handling hassle during assembly. MyData is one of the few exceptions that can pick up parts from short sections of taped parts. But, we only use this company for prototypes (20 boards.) How many connectors or large passives are thru-hole and must be wave soldered or hand soldered? Unless your company has it's own SMT assembly line (fixed conveyor width), and because different assembly houses have their own requirements, You're generating data that is almost always nuked in CAM during fabrication.
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Forum Post: RE: Are there any specific gotchas for using OCEAN with SKILL++?
That's great. Thanks.
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Forum Post: RE: Exporting ADE-L Design Variables into a CSV file
Yes, you're right, I must have tried it with no ADE-L session open, so asiGetDesignVarList(asiGetCurrentSession( )) had to fail that time, but did not when I tried later with an open session. Now I have a solution which does import and export design variables, nicely integrated into ADE as two new menu items, which was very easy to implement, thanks to your code snippets in this and the Custom IC SKILL forum. And thanks for your hint to better migrate to ADE Explorer/Assembler. We actually use it in new projects, but my question came up when I had to re-simulate a rather old design. But of course, converting our old simulation states to ADE Explorer and then using the already existing Export/Import functionality might have been the faster and easier solution to my question...
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Forum Post: RE: DRC: shape to route keepout spacing
Hi It is defined as Shape to route keepout on all layers.
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Forum Post: library path issue
Hello Everyone, I am new cadence pcb designing environment. I am try to create a pcb in cadnce from very scracht. I started with Design Entry HDL and created a few components schematic and want to transfer it to .brd file. but when I try to export physical, I received the following message.Could anyone help me in this regards.
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Forum Post: RE: Noise Analysis for Modulated Noise Using Verilog-A Modelling
You cannot simulate modulated noise with a simple noise analysis. Use either pnoise or hbnoise.
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Forum Post: RE: Does hbnoise support the ideal switch from analogLib?
If it works with pss/pnoise but doesn't with hb/hbnoise and also produces a warning about an arithmetic exception in this case, I would say that it's likely a bug in the hbnoise analysis. I suggest that you examine if the problem also exists in the most recent Spectre release and report it to Cadence Support if it does.
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