Thank to all, I have to update the blog that the problem is now solved. just by updating the default editor path to any editor. I set it C:\Windows\notepad.exe.Now it works.
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Forum Post: RE: library path issue
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Forum Post: Unable to generate artwork because of polarity issue & unable to delete layer.
Hello, I am working with a 4 layer board and trying to generate the gerber files required for fab. I am having issues with generating the artwork for my GND layer. It gives me the following error: "ERROR: aborting film - Layer polarity of layer ETCH/L2_GND does not match film polarity of Positive. DRC may be unreliable." I tried various ways to fix that first, but it didn't work. Now I am trying to delete that layer and create a new one but it also doesn't let me delete that saying the following, even though I deleted the copper pour from that layer and there are no elements left on that layer. "Layer being deleted: ETCH/L2_GND (-5802.437 -1990.874) TEXT LINE: L2 Gnd (-5802.437 -1990.874) TEXT: L2 Gnd (1220.232 2564.340) DYNAMIC SHAPE: Gnd, Boundary/L2_Gnd (1008.084 2352.192) SHAPE(auto-generated): Gnd, Etch/L2_Gnd " Can anybody please lend me some help or direct me to the solution, I am very lost at this point. Any help would be really appreciated!
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Forum Post: RE: Unable to generate artwork because of polarity issue & unable to delete layer.
Go to Setup>Cross Section, expand the Physical settings and uncheck all of the Negative Artwork boxes, OK that and update the Shapes before generating artwork.
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Forum Post: RE: DRC: shape to route keepout spacing
You can't "completely" fix this because you have placed the Shape of the Fiducial and then surrounded that with a Route Keepout. Route Keepouts don't allow Shapes so you get the error. Waive the DRC is about as good as it gets. You could add a "Shapes Allowed" Property to the Route Keepout but this could, potentially, allow "any" shape into the Route Keepout, which would be undesirable.
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Forum Post: RE: DRC: shape to route keepout spacing
Here's my fiducial - 1) Top etch pad; in the pad editor I specify a 'Keeput' region (to keep etch away from it); Make sure the soldermask gets pulled back to expose the pad and clearance to copper too. 2) Have a DFA Place Boundry defined for it the size of the soldermask pullback 3) In the layout I have a DFA Constraint to keep any components away from them Easy, quick, simple. Good day.
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Forum Post: RE: DRC: shape to route keepout spacing
Hey, after I have seen your comment. I went back into my fiducial to see how I made my part. Because I never get those DRC;s. I made the part using a mechanical SMD pin instead of a shape.
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Forum Post: K Stability Factor Simulation Results Do not show up
Hi, I have designed an LNA and am going to check the k Stability factor. When I run the s-parameters I plot the k-stability factor, but nothing shows up and the screen is black and nothing is there. So, any suggestion how can I fix this issue? Regards, Mehdi
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
Hi Medhi, You'll need to provide some more information, because I just did this and it worked fine - and I'm not aware of this being a recently reported issue. So please can you answer these questions: Which IC subversion are you using? This is in Help->About (please give the full number, not just the first part) Which spectre version are you using (this will appear at the top of the spectre.out log file in ADE)? Assuming you're using spectre, that is... Which ADE flavour are you using? ADE L, XL, Explorer or Assembler? Or if not ADE, how are you running the simulation? How are you plotting the "k-stability factor" - explain precisely how you are doing this Please copy and paste the analysis statements from the input.scs file in ADE (the bottom part of the input.scs), particularly the "sp" analysis lines. Are there any errors that appear in the CIW when you do this? Regards, Andrew.
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Forum Post: RE: How to reuse circuit INITIAL conditions (at simulation time t=0) at multiple instants during a single transient run
Dear Andrew, I think running multiple new transient simulations will take more time as each time it has to find DC convergence, initial condition (apart from other stuffs needed to be done at the beginning). Is there a way we can run multiple new transient simulations yet, we can avoid the initial repetitive stuffs so that it can be fast like a single tran simulation.
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
Which IC subversion are you using? This is in Help->About (please give the full number, not just the first part ) IC6.1.7-64b.500.18 Which spectre version are you using (this will appear at the top of the spectre.out log file in ADE)? Assuming you're using spectre, that is... Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 15.1.0.803.isr18 64bit -- 21 Jun 2017 Copyright (C) 1989-2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: mehdina94rm Host: amml.ece.neu.edu HostID: A81673C PID: 248590 Memory available: 82.7415 GB physical: 133.5396 GB Linux : CentOS Linux release 7.5.1804 (Core) CPU Type: Intel(R) Xeon(R) Gold 6136 CPU @ 3.00GHz Socket: Processors [Frequency] (Hyperthreaded Processor) 0: 0 [1307.2] ( 12 ), 1 [1199.9] ( 13 ), 2 [1200.6] ( 14 ) 3 [1199.9] ( 15 ), 4 [1199.9] ( 16 ), 5 [1199.9] ( 17 ) 6 [1209.6] ( 18 ), 7 [1199.9] ( 19 ), 8 [3599.9] ( 20 ) 9 [1199.9] ( 21 ), 10 [1200.1] ( 22 ), 11 [1200.1] ( 23 ) System load averages (1min, 5min, 15min) : 5.0 %, 5.7 %, 5.9 % Hyperthreading is enabled Simulating `input.scs' on amml.ece.neu.edu at 4:15:16 PM, Mon Nov 4, 2019 (process id: 248590). Current working directory: /ECEnet/home/student/mehdina94rm/Sim/LNA_diff_matching_finalized_tb/spectre/config/netlist Command line: /ECEnet/Apps1/linux/cad12/tools/cadence/MMSIM151/tools/bin/spectre \ -64 input.scs +escchars +log ../psf/spectre.out -format psfxl \ -raw ../psf +lqtimeout 900 -maxw 5 -maxn 5 Loading /ECEnet/Apps1/linux/cad12/tools/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ... ... Time for NDB Parsing: CPU = 454.093 ms, elapsed = 1.14059 s. Time accumulated: CPU = 492.094 ms, elapsed = 1.1406 s. Peak resident memory used = 53.5 Mbytes. The CPU load for active processors is : Spectre 0 (8.8 %) 1 (6.1 %) 2 (23.5 %) 3 (15.9 %) 6 (16.1 %) 7 (12.4 %) 8 (100.0 %) 9 (4.5 %) 11 (12.9 %) 13 (1.7 %) 16 (1.8 %) 21 (2.7 %) 22 (2.7 %) Other Reading link: /ECEnet/Apps1/linux/cad12/tools/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/discipline.h Reading file: /ECEnet/Apps1/linux/cad12/tools/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams Reading link: /ECEnet/Apps1/linux/cad12/tools/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.h Reading file: /ECEnet/Apps1/linux/cad12/tools/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams Time for Elaboration: CPU = 152.351 ms, elapsed = 159.82 ms. Time accumulated: CPU = 644.588 ms, elapsed = 1.30056 s. Peak resident memory used = 81.9 Mbytes. Time for EDB Visiting: CPU = 90.327 ms, elapsed = 90.5421 ms. Time accumulated: CPU = 735.056 ms, elapsed = 1.39124 s. Peak resident memory used = 97 Mbytes. Notice from spectre during topology check. Only one connection to the following 56 nodes: I21.M5|avC2 I21.M5|avC1 I21.M7|avC2 I21.M7|avC1 I21.M17|avC2 Further occurrences of this notice will be suppressed. No DC path from node `I21.M5|avC2' to ground, Gmin installed to provide path. No DC path from node `I21.M5|avC1' to ground, Gmin installed to provide path. No DC path from node `I21.M7|avC2' to ground, Gmin installed to provide path. No DC path from node `I21.M7|avC1' to ground, Gmin installed to provide path. No DC path from node `I21.M17|avC2' to ground, Gmin installed to provide path. Further occurrences of this notice will be suppressed. Global user options: reltol = 1e-06 vabstol = 1e-08 iabstol = 1e-13 temp = 27 homotopy = 7 limit = delta compatible = spice2 gmin = 1e-12 rforce = 1 maxnotes = 5 maxwarns = 5 digits = 5 cols = 80 pivrel = 0.001 sensfile = ../psf/sens.output checklimitdest = psf save = allpub tnom = 27 scalem = 1 scale = 1 Scoped user options: Circuit inventory: nodes 10869 bsim3v3 172 capacitor 3468 diode 472 inductor 20 isource 2 port 3 resistor 17819 transformer 2 vcvs 2 vsource 3 Analysis and control statement inventory: info 6 sp 1 Output statements: .probe 0 .measure 0 save 0 Notice from spectre. 54 notices suppressed. Time for parsing: CPU = 33.381 ms, elapsed = 36.0088 ms. Time accumulated: CPU = 768.582 ms, elapsed = 1.42739 s. Peak resident memory used = 104 Mbytes. ~~~~~~~~~~~~~~~~~~~~~~ Pre-Simulation Summary ~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~ Warning from spectre. WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format. ************************************************** S-Parameter Analysis `sp': freq = (2 GHz -> 3 GHz) ************************************************** Notice from spectre during DC analysis, during SP analysis `sp'. GminDC = 1 pS is large enough to noticeably affect the DC solution. dV(I21.I9|M2_10__rcx.b1d) = 14.1994 nV Use the `gmin_check' option to eliminate or expand this report. DC simulation time: CPU = 82.559 ms, elapsed = 82.7818 ms. sp: freq = 2.023 GHz (2.84 %), step = 4.653 MHz (568 m%) ... sp: freq = 2.992 GHz (99.4 %), step = 6.882 MHz (568 m%) sp: freq = 3 GHz (100 %), step = 7.529 MHz (568 m%) Accumulated DC solution time = 80 ms. Intrinsic sp analysis time = 820 ms. Total time required for sp analysis `sp': CPU = 2.88472 s, elapsed = 3.30678 s. Time accumulated: CPU = 3.69166 s, elapsed = 5.28976 s. Peak resident memory used = 131 Mbytes. modelParameter: writing model parameter values to rawfile. Opening the PSF file ../psf/modelParameter.info ... element: writing instance parameter values to rawfile. Opening the PSF file ../psf/element.info ... outputParameter: writing output parameter values to rawfile. Opening the PSF file ../psf/outputParameter.info ... designParamVals: writing netlist parameters to rawfile. Opening the PSFASCII file ../psf/designParamVals.info ... primitives: writing primitives to rawfile. Opening the PSFASCII file ../psf/primitives.info.primitives ... subckts: writing subcircuits to rawfile. Opening the PSFASCII file ../psf/subckts.info.subckts ... Aggregate audit (4:15:21 PM, Mon Nov 4, 2019): Time used: CPU = 4.07 s, elapsed = 5.78 s, util. = 70.4%. Time spent in licensing: elapsed = 34.5 ms. Peak memory used = 141 Mbytes. Simulation started at: 4:15:16 PM, Mon Nov 4, 2019, ended at: 4:15:21 PM, Mon Nov 4, 2019, with elapsed time (wall clock): 5.78 s. spectre completes with 0 errors, 1 warning, and 7 notices Which ADE flavour are you using? ADE L, XL, Explorer or Assembler? Or if not ADE, how are you running the simulation? ADE L How are you plotting the "k-stability factor" - explain precisely how you are doing this . Results --> Direct Plot --> Main Form --> sp --> Kf --> plot Please copy and paste the analysis statements from the input.scs file in ADE (the bottom part of the input.scs), particularly the "sp" analysis lines. ps=0.7u*2+(700.0n) nrd=0.3u/(700.0n) nrs=0.3u/(700.0n) \ par1=((1)*(1)) I10 (net032 vss) isource dc=500u type=dc I5 (net31 vss) isource dc=500u type=dc I29 (net13 vss net18 net14) ideal_balun PORT3 (LNA vss) port r=50 type=dc PORT4 (out vss) port r=50 num=2 type=dc E0 (LNA vss RFout\- RFout\+) vcvs gain=1 E2 (out vss RFout\- RFout\+) vcvs gain=1 simulatorOptions options reltol=1e-6 vabstol=1e-8 iabstol=1e-13 temp=27 \ tnom=27 homotopy=all limit=delta scalem=1.0 scale=1.0 \ compatible=spice2 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 digits=5 \ cols=80 pivrel=1e-3 sensfile="../psf/sens.output" checklimitdest=psf sp sp ports=[PORT1 PORT3] start=2G stop=3G dec=1000 donoise=yes \ oprobe=PORT3 iprobe=PORT1 annotate=status modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=allpu Are there any errors that appear in the CIW when you do this? No errors.
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
1. You are using an extremely outdated version of Spectre. (15.1). The latest version is 19.1. You should upgrade to at least 18.1 2. You have two ports (PORT3 and PORT4) in your netlist. PORT3 (LNA vss) port r=50 type=dc PORT4 (out vss) port r=50 num=2 type=dc In your sp statement, you list a port that is not in your netlist. Where is PORT1?: sp sp ports=[PORT1 PORT3] start=2G stop=3G dec=1000 donoise=yes \ oprobe=PORT3 iprobe=PORT1 annotate=status Best regards, Tawna
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Forum Post: RE: Orcad Capture - Slow Graphics response on windows 10
Is there no fix for this issue yet? The toolbar icons refreshing every now and then is annoying -- I have all toolbars from View > Toolbar checked. Working on Windows 10 version 1903 (OS Build 18362.356) with all the latest drivers. ORCAD version 17.2-2016.
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Forum Post: RE: Renaming instances with a pattern in its name to a new pattern
Thanks for the prompt response Sheppie, let me check on this.
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Forum Post: RE: Renaming instances with a pattern in its name to a new pattern
Thanks for your response William, but as I am still novice at SKILL, let me check the solution from Sheppie first
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Forum Post: Transfer occurrence property to instance property
Hello Group, I'm trying to transfer all attributes available in occurrence to instance property using an option Accessories -> Transfer Occ. Prop to Instance. The purpose of this exercise is to maintain the information in the instance and occurrence property the same, which is currently not the case. While performing this, the parts information is copied correctly but the Title block information is not reflecting. Any suggestions?
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
Tawna, The missing port is probably just because this is a snippet of the netlist; if the port was really missing, the sp analysis would fail (I checked). Mehdi, I ran with the exact same version of MMSIM and IC that you are (Tawna's right, the MMSIM version is old, although the hot fix you're using is less than 2.5 years old, compared with the IC version which is about 1.5 years old - so compared with much that we see here, it's not that bad...). It works fine for me - I even set up the sp analysis the same as you did (same start and stop frequencies, turning on noise, and so on). By the way, your reltol/vabstol/iabstol are way too tight. You really should not need reltol of 1e-6 except in very rare situations, and even then only for transient simulations where you need very high dynamic range (typically you'd have to be doing an FFT of the results, and even then you'd need to ensure that it's not your measurement accuracy that is wrong). This is a good way of unnecessarily slowing down the simulations for little advantage. However, that's unlikely to be the issue here. The simulation ran in a few seconds, so that's more of a point for future reference. Can you try pasting this expression into the calculator and then plotting that to see if this works? kf(sp(1 1 ?result "sp") sp(1 2 ?result "sp") sp(2 1 ?result "sp") sp(2 2 ?result "sp")) Regards, Andrew.
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Forum Post: RE: How to reuse circuit INITIAL conditions (at simulation time t=0) at multiple instants during a single transient run
Given that initial conditions are applied during the DC before a transient analysis, then no. They are used to intentionally force the DC solution to something other than what it would find normally, but that's work that has to be done and can't be avoided. Yes, it could have avoided the initial netlist read maybe, but if you did this using a parametric analysis in ADE L or a variable sweep in ADE Explorer, it can do this within a single invocation of the simulator and that would be saved. It's unclear to me how this would (or could) be any faster - the DC should be very quick if the initial conditions match the circuit... The best thing would be to contact customer support so somebody can look at your actual circuit and understand what's going on here. Andrew.
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Forum Post: RE: Does hbnoise support the ideal switch from analogLib?
I checked the netlist with the latest Spectre version, and it also still produces the warning. I think the warning is benign, but I filed CCR 2180892 to get this addressed. I found some earlier similar requests to R&D but thought a specific request for this issue would make sense. Note that it's nothing to do with the switch (relay) components as it still happens if they are commented out. Nor is it anything to do with the use of the noise file source. Regards, Andrew.
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Forum Post: RE: Does hbnoise support the ideal switch from analogLib?
Hi, Thanks for taking the effort to check and for filing the ticket. BTW, I don't see an issue if I remove the divider(e.g. the circuit below). There is no exception reported and the results are as expected. I have also used hbnoise with a number of other circuits without any problems. (This is why I unjustifiably assumed that the switch was the issue. It was the most exotic component in my previous circuit :) Nagendra
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Forum Post: RE: Does hbnoise support the ideal switch from analogLib?
Hi Nagendra, Actually this seems to be dependent upon E0 - the first of the two vcvs in the circuit. If I remove it, or reduce the gain to 1, or remove the min and max options (of course, this alters the behaviour of the circuit) the arithmetic exception warning goes away. Hopefully we'll clarify this if R&D can look at it. Regards, Andrew.
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