This is because of the way partial capacitances are defined. e.g., Cgs is the change in the charge on the gate (g: first subscript) for a unit change in the voltage on the source (s: second subscript). When defined this way, capacitance will come out negative (even for a regular capacitor) because, if you increase the source voltage, there will be more positive charge on the source terminal and negative charge on the gate terminal. For the "conventional" capacitance definition, use Cgg, which is the change in the charge on the gate (g: first subscript) for a unit change in the voltage on the gate (g: second subscript). Asymmetry comes from nonlinearity and the way channel charge is apportioned between drain and source. Chapter 7 in the book below has the details. Operation and Modeling of the MOS Transistor (The Oxford Series in Electrical and Computer Engineering) 3rd Edition by Yannis Tsividis (Author), Colin McAndrew (Author) Nagendra
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Forum Post: RE: spectre captab: 1) negative capacitance 2) not reciprocal values
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Forum Post: RE: Does hbnoise support the ideal switch from analogLib?
Interesting. Thanks! After some more tinkering, I found that, if it functions as a divider, hbnoise has a problem. With the same component values, if I initialize the capacitors to zero volts, the output waveform is perpetually zero because the same voltage keeps circulating around the loop. In this case, hbnoise does not show any exception. The noise is of course zero. But if I initialize both capacitors 1V so that it functions as a frequency divider, hbnoise has arithmetic exception. I'll await the results from the Cadence team. Regards Nagendra
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Forum Post: RE: Ocean parametric sweep fail due to memory
Hi Andrew Thanks for your suggestion with the env option. This didn't change the memory growth. So I have contacted cadence support. Thanks, Peter
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Forum Post: Skill code for snap to grid an entire library
Hello, I am in need of a skill function or function to snap to grid an entire library, polygons, paths, texts, mosaics ... Any help would be appreciated. Thanks in advance.
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Forum Post: Extract Library from Design Cache
Hi All, Is there a way to extract the library symbols from the design cache in OrCAD Capture? I tried to modify a part but it looks like it will not let me because it cannot find a corresponding library entry. I inherited a design file that does not have any library files.
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
Andrew and Tawana, Thanks for your comments. I have checked with school and they will upgrade it. But I am not sure if thats the problems since I was previously running it even with the older cadence version. Regarding the missing Port, I have to mention that I have a couple of ports in other parts of the circuit but not used in this simulation. So it will not be an issue since the SP analysis is running and I can get the S parameters without any issue. The only issue is the result of Kf. I have checked the equation and that is exactly the same as what you mentioned above, BTW I copied yours into my calculation and the result is the same and nothing shows up.
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Forum Post: RE: Extract Library from Design Cache
I just discovered that I was in error when I could not edit a part without the library. Apparently there was an issue with the bounding box: Invalid rectangle. Redraw from top-left to bottom-right. I still would like to know how to extract a library if one does not exist from the design cache if possible.
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Forum Post: RE: Extract Library from Design Cache
You can copy / paste items from the Design Cache into a Library using Edit Copy / Paste, or control+C / V. In current releases, an arbitrary selection of Parts and Symbols from the Design Cache is supported, in past releases, only a selection of Parts, or Symbols, (rather than a "mix") from the Design Cache was supported for pasting.
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Forum Post: Feasibility Analyses In Cadence ADE GXL
Hello, I have recently worked with Circuit optimization using Cadence ADE GXL. I used both the Global and the Local optimizer to final size my circuit against PVT corners, seems everything is ok for me. I read in Cadence documentation help about the Feasibility Analyses, but I didn't understand the purpose of it or what is the difference between it and the global or local optimization? Anyway, I have tried to run it and see it but I am receiving this error message, I kindly need your help to solve this issue and to understand the purpose of running the Feasibility analyses Thank you
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Forum Post: RE: Extract Library from Design Cache
Thanks. That worked.
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Forum Post: OrCAD Capture: Edit Multiple Pins
When you are making a schematic symbol, is there a way to edit multiple pins to change their properties? For example, say I have 25 pins that have a shape of line but I want to change them all to short or zero length . I have only been able to only select one at a time to change them individually. It takes a while to change multiple pins that way. In other programs like EAGLE and Altium, they have the ability to make many quick changes. EAGLE can allow you to select a change tool and you can just click on the ones you want changed and then they change and Altium allows you to select as many objects that are the same and you can change them all with a simple selection to the new type. Does OrCAD have anything like this?
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
Can you plot anything else from the Direct Plot form for the sp analysis? For example, plotting s11 or s22, or any of the other metrics? Is it just Kf that is the problem? Regards, Andrew.
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Forum Post: Undertermined SW version
I updated to latest hotfix S060 and for installed version shows-undefined000, any idea why this doesn't work?
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Forum Post: Using Op Amps in PSpice Circuit builder.
I am building a circuit using op amps in pspice. The op amp layout in pspice is what you would expect, the little triangle representing one (1) op amp. However, the components I will be using to actually build the op amp are two (2) op amps on one single 8-pin DIP chip. when I try to create the PCB it is representing each op amp as its own chip. How do I combine the op amps to represent one 8-pin DIP when I am trying to build the PCB?
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Forum Post: PDF Export
I want to export PDF using the PDF export from File drop down. This works fine when I have just the base 17.2 version installed. Any idea how to fix? SERVER ERROR:orPrmRequestDispatcher_executeLocal: Server method failed - Internal Server Error
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
Andrew, I can plot S11, S21, S12, S22, NF. But I cannot plot Kf and B1f or even Z parameters.
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
Here is the error that I get when I plot z-parameters: ERROR (WIA-1006): Unable to plot expression because it does not evaluate to an object that can be plotted, like a waveform or parametric wave. See the Visualization & Analysis Tool documentation for information about the types of objects that can be plotted in Visualization & Analysis Tool. Only the expressions that evaluate to those objects can be plotted. *Warning* Wave1 is not a waveform object that can be displayed and will be DELETED automatically. name: "Z11 magOhm"
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Forum Post: Mapping for DPAR_ param name
I am trying to call a netlist procedure and need to create different netlist based on the parameter set from maestro run . But i can only get parmeter names like DPAR_1 , DPAR_2 . How can i get the mapping to orignal parameters in my cell ? Is there a mapping skill function available , which i can use inside my skill netlist procedure ?
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Forum Post: RE: Mapping for DPAR_ param name
I don't see why you would be getting these names - what exactly are you doing? Please give precise details (ideally with the code) so that we can have some chance of understanding what you're doing. Knowing why you're doing it is important too, because maybe there's a better way of achieving what your end goal is? Andrew.
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Forum Post: RE: K Stability Factor Simulation Results Do not show up
Can you do the following tests in the CIW after running the simulation and trying to plot in the direct plot form: outputs(?result 'sp ?map nil) zpm('sp 1 1) kf(sp(1 1 ?result "sp") sp(1 2 ?result "sp") sp(2 1 ?result "sp") sp(2 2 ?result "sp")) and paste here exactly what it shows in the CIW - the pasted commands and output/errors between them. For me it shows: outputs(?result 'sp ?map nil) ("s11" "s21" "s12" "s22" "cy11" "cy21" "cy12" "cy22" ) zpm('sp 1 1) srrWave:0x32b12020 kf(sp(1 1 ?result "sp") sp(1 2 ?result "sp") sp(2 1 ?result "sp") sp(2 2 ?result "sp")) srrWave:0x32b12190 Andrew
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