Checked the pin properties. Unfortunately, even after updating the pin thermal contact type and width, nothing happens..
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
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Forum Post: RE: Shape to route keepout gap?
Oops, are you saying that artwork is ot exctly what i see? What is the REAL thing thath drc check use? On some board, i haveto GARANTY a certain spacing minimal value (legal requirement). We already add 10µ to this value to avoid calculation errors but if allegro use different one....
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
Are there any properties on the pin? If not try adding: Dyn_Thermal_Con_Type = ORTHOGONAL Dyn_Thermal_Best_Fit = TRUE No_Shape_Connect = False See if any of these settings change the connection. Also as a test, can you route on the pour to the pin?
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
Tried your suggestion: Dyn_Thermal_Con_Type = ORTHOGONAL Dyn_Thermal_Best_Fit = TRUE No_Shape_Connect had only "true" option --> didn't chose anything. I am able to route a line from that pin to another (with same net). Still no thermal relief:
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Forum Post: United Kingdom 17.4 Orcad Users
Hi All, Having downloaded and installed orcad version 17.4 I am ready to "play with the new features" however I am still waiting for my new Licence file. I have contacted my distributor who informs me that they are waiting for Cadence to release the keys. Is there anyone else in the United Kingdom that is waiting for there licence files. This is frustrating I actually downloaded it nearly three weeks ago but still no licence file I have checked my junk email bin to make sure it hasn't found its way in there.
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
I am assuming this is a dynamic shape - Once the Properties are set try updating shape: Global Dynamic Shapes Parameters - Update to Smooth -> Force Update Note: the thermal spokes may not be forming because the shape does have enough room around the pin, can you grow the shape a little in width by the pin? Also try: Dyn_Thermal_Con_Type = 8_WAY
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Forum Post: RE: Any Way to identify double hits (Via)?
I'm having trouble as Allegro PA3100 16.6 SP115: W- *WARNING* context read failure: can't read 64-bit context on 32-bit platform E- *Error* loadContext: context I/O failed - "findDoubleHitHoles_public.cxt" Starting new design... 17p2 s061 gives me: *Error* loadContext: could not open file - "64bit/findDoubleHitHoles_public.cxt"
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
I wonder if it's related to the dra file of that specific part, or maybe to the constraint manager. I have another 1 more component in my circuit that has the same problem.
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Forum Post: RE: Any Way to identify double hits (Via)?
I need to keep 16.6 running until Mentor Graphics updates their translator to Expedition/P*DS to deal with the padstack changes, etc.
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Forum Post: RE: Any Way to identify double hits (Via)?
Sorry about the 17.2 question. I found that my 64bit folder copy of the cxt file didn't go through. Now it works. Does anyone have a 32-bit cxt file that works for 16.6?
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Forum Post: RE: Any Way to identify double hits (Via)?
community.cadence.com/.../findDoubleHitHoles_5F00_public.zip
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Forum Post: RE: Shape to route keepout gap?
I believe what this means is that if you make the correct size keepout, the artwork exports voids will be that exact size. Showing element on the shape void in allegro with give you the incorrect radius size... as oldmouldy said, allegro adds a gap to avoid rounding issues. So , instead show element on the keep out you've created, that should be the size you intend to use. There is no DRC check (that i know of) for shape to route keepout spacing.
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Forum Post: Altium to OrCAD 17.2 Translation Issues
Hello all, I have an issue for which I cannot find a solution. I have translated an Altium schematic using File->Import->Altium Schematic Translator . Under the dialog box, there is a help file that explains what needs to be done in both Altium and OrCAD. I saved the files as the Advanced Schematic binary (*.SchDoc) as directed. There is a PCB Project file (*.PrjPCB) and a valid structure file (*.PrjPCBStructure) . I converted all of the Altium schematic pages to custom so the page sizes will be correct. Almost everything translated properly except the few things that is indicated that it cannot understand such as the signal harness where the signals are combined into one fancy line. That is not an issue for me at the moment. The main issue I have is the non-aliased nets reverted to an OrCAD default naming style, something like N00027 from say Q6_1. This is not necessarily a problem either. I know that OrCAD capture cannot change the names of the nets back to the Altium style. The problem that I know I will have is when I try to link the PCB to the schematic. I know that I will have to re-run the Tools->Create Netlist... to recreate the netlists. This will be the problem. When I translated the Altium PCB to OrCAD, I followed the same instructions that were found Import->Translators->Altium PCB... . The help file under that dialog box explains that you need to save the PCBs as a PCB ASCII File (*.PcbDoc) . I checked the Create Individual Symbol Definitions and Derive Connectivity check boxes as well as the Extended radio button. The board was completely translated. All of the traces/nets were translated as they are on the Altium PCB. The issue that I have is the translated PCB nets do not match because none of the non-aliased nets changed into a default net like in the schematic. So the question is, how do I change the PCB to make the traces/nets conform to the schematic net naming so I can recreate the netlists? Any help would be greatly appreciated.
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
Still not connecting..
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
A couple other things to check Are the pins outside of the Route Keepin/All Shape? ( Long shot but had to ask :-) ) Thermal Clines create DRCs outside the Keepin so they would not be generated. Is there a Route Keepout Shape with the SHAPES_ALLOWED Property over the pins? SHAPES_ALLOWED Property on Keepout shapes would allow Dynamic Shapes but not the Thermal Clines. Hope this helps, Mike Catrambone
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
Try this - Edit the pin and set the DYN_THERM_CON_TYPE to CDN_All and "Full contact" and see if it pours over the pad. If it does, then follow Mike's suggestion If it won't pour over it's not the pad issue, it's more likely the shape parameter. (e.g. if you make the shape larger will it flood/spoke? Good day.
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Forum Post: RE: TH pin does not connect to a shape of the same assigne net
Another lookie place - Edit Constraints/Properties/Component/Pin Properties - look into the components giving you issues and see if the part is set NOT TO CONNECT. Never used this, but someone might have set it incorrectly when building the part(s).
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Forum Post: RE: Altium to OrCAD 17.2 Translation Issues
Hi, As long as the PCB connections are the same as the netlist connections, it shouldn't be a problem, and the PCB will update to the new netnames. So if your PCB was N00001 and the new netlist called it CLKOUT (or whatever), as long as the connections (pin to pin to pin, AND!!!! the same reference designators) it will simply re-assign the net to the new netlist. Are you trying to do this conversion all at once (convert the schematic, pcb layout, and converge), or did you translate each on separately and then try to import the new netlist? I ALWAYS do things separately (just my mode). Regards.
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Forum Post: regular pad flash and odb++ output
We flash a 5 mil pad on the top and bottom layers for a non-plated hole. A larger pad is there in Allegro 17.2 to keep copper away from the hole. When we gerber out, the large pad is replaced with the 5 mil pad that gets drilled away. We cannot get ODB++ out inside Allegro to make this substitution. Is anyone doing some thing similar ? Thanks Les
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Forum Post: RE: regular pad flash and odb++ output
Hi Les, This is the 'old' way of doing what you want. What I do is have the 5mil pad, but in the padstack set the 'Keep Out' to be the size you want the copper to be pulled back. You don't need to set a 'large' pad for keepaway any longer. FYI - I don't set any "thermal pad" or "anti pad" definitions either since I don't use negative planes.
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