[quote userid="403514" url="~/cadence_technology_forums/f/pcb-design/43001/altium-to-orcad-17-2-translation-issues/1364115#1364115"]Are you trying to do this conversion all at once (convert the schematic, pcb layout, and converge), or did you translate each on separately and then try to import the new netlist? I ALWAYS do things separately (just my mode).[/quote] I have not actually tried to make a new netlist yet as I have not finished fixing the schematic. I assumed that when I made the netlist and imported it into the PCB that it would cause conflicts based on the nets being different. I also did everything separately, first the schematic and then the PCB. I have to say, the PCB translated perfectly other than a couple of silk images that did not convert. I will make the necessary changes to the schematic and then I will report back on whether I had success or not. Thanks for the information.
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Forum Post: RE: Altium to OrCAD 17.2 Translation Issues
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Forum Post: RE: Altium to OrCAD 17.2 Translation Issues
Yep. As long as your net connectons are the same, and your reference designators are the same, it should import clean (or close). We change net names all the time and it simply renames the nets in the layout. (I add a bunch more net information once I get going along so it's easier to follow in design reviews). Good luck. Be interested in seeing your successes.
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Forum Post: RE: Is there a way to eliminate undesired data from a psfxl file to save area in a maestro output?
Shawn - thank you for your reply. I don't think that will do what I want it to do, which is keep the data accessible from maestro, so I can see the outputs all listed by corners, the mins and maxes and which corners meet the specs. I want to keep that but delete the 10000 other signals that I don't care about:
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Forum Post: How to sort instances in layout based on instance name?
Hi, How can i sort instances in layout based on instance name? For example, if i've 50 instances named "inv ", how do i sort them all based on the instance name in an ascending/descending order? Is there an built-in function that can do this? Or anyone has got a SKILL solution/approach to this? Thanks Ram
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Forum Post: RE: regular pad flash and odb++ output
Thank you. I guess we need to update are NPTH padstacks .... Les
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Forum Post: RE: Altium to OrCAD 17.2 Translation Issues
Save them as ASCII. Don't save the files as " Advanced Schematic binary "
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Forum Post: RE: regular pad flash and odb++ output
Why not use the hole-to spacing constraint?
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Forum Post: RE: Can I link a inductor part to resistor part by using CIS variant design?
Thank you oldmouldy, I am very happy to have you or steve answering my question. I will try it.
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Forum Post: RE: Is there a way to eliminate undesired data from a psfxl file to save area in a maestro output?
If you're OK with keeping the scalar results but none of the waveforms, you can do that over the history in the history tab of the data view assistant by using Right Mouse->Delete Simulation Data. If you want to keep some of the waveforms, then one way (it's going to need a bit of scripting) would be to use the srrextract.sh utility that's in IC618 and ICADVM181. For each leaf psf directory, you could do: srrextract.sh -database psf -dataset tran-tran -signal out1 -signal out2 -signal out3 -o psfnew You could then move psfnew to be psf (this will only work if you only care about just one analyse's results), or replace the individual PSF XL files in the original psf directory with the files from the new directory (note the names may be tran.tran.tran* in the original and tran.tran* in the new, so you'd need to keep the original names if you do this). Back up your data first before trying this! (or try it on something small that doesn't matter first). Regards, Andrew.
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Forum Post: RE: How to sort instances in layout based on instance name?
By sort, do you mean to sort them physically (so they are placed in order, left to right or top to bottom)? Or do you just mean sort a SKILL list of such instances? If it's the latter, then: listOfInsts=sort(listOfInsts lambda((a b) minusp(alphaNumCmp(a~>name b~>name)))) Regards, Andrew.
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Forum Post: RE: ADE L simulation gave error!
First of all, you posted this question in the Feedback, Suggestions and Questions forum which is for issues with the forum itself, not for technical questions. Luckily I monitor that forum and move any mis-posted threads from there into a more suitable forum. I don't know what this "IC-gpdk" library is, but it sounds as if it's missing the stopping views. Can you bring up the library manager, navigate to IC-gpdk and cell nmos, and then post a screenshot of what you see? Regards, Andrew
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Forum Post: RE: How to sort instances in layout based on instance name?
Yes, sort them physically and place them in a row. Thanks Ram
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Forum Post: RE: How to sort instances in layout based on instance name?
I don't have any code that does that, but having sorted the list of instances as above, you could step through the list updating the ~>xy of each instance to an incrementing location, so it would be easy enough to write... Andrew.
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Forum Post: RE: spectre captab: 1) negative capacitance 2) not reciprocal values
I really try to understand this. One of my problems with it is that how can we speak about charge change if we regard only the capacitance (one side has to be driven with a voltage source and the other grounded at least), or if we take the whole transistor into account, than we see the transistors effect in the charge change, e.g. if the gate voltage is increased, than charges will be drawn from the drain and its capacitances, which is much more than the cap itself. What I am looking for, and I believe, but can not be sure, that other designers are also curious about the capacitances what one would add to the DC model to get the AC behaviour. I often derive an analytical model of the circuit I am designing for optimization, and for the verification of such models I need the caps from circuit design textbooks. Do you have any workaround how to get reliable capacitance values for that?
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Forum Post: RE: United Kingdom 17.4 Orcad Users
17.4 was officially released yesterday the 18th November and channel partners are in the process of issuing licenses but you can imagine this is a large task as each one needs to be checked. You should hopefully receive this in the next few days.
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Forum Post: RE: ADE L simulation gave error!
Hello Andrew, Thank you very much for moving the question, Please see attached figure. Regards
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Forum Post: RE: ADE Assembler - Changing the Maximum Jobs while a Run is In Progress
This has always worked for me (at least in ADEXL). Did you select the "Start Immediately" checkbox?
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Forum Post: RE: ADE Assembler - Changing the Maximum Jobs while a Run is In Progress
Thanks for your input Frank. Yes I also remember it working on ADEXL. I just retried by presetting the "Start Immediately" checkbox to both values before re-running, but this did not resolve the issue. I had a look at the description of the "Start Immediately" setting in the ADE Assember user manual, but its function is not very clear to me.
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Forum Post: How to define via structure in allegro /Orcad 17.x
Hello I just migrated from 16.x to 17.x , finding difficulty in Defining via structure . in 16.x it was easy "select Cline,via and create via structure and then click on fan-out use the defined via structure for similar type component " Now in 17.x its saving in .xml format and when go for fan out define via structure its not available from the drop down menu . I am not clear with preserve property (refer image) Anyone could help me on this ? I googled it but didn't get proper explanation ( community.cadence.com/.../highspeed_5f00_via_5f00_structures) Thanks GK
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Forum Post: RE: 17.4 Design Sync, parts without footprint
I had the EXACT same issue; error-for-error. The thing that was really causing my error was that I was syncing to a design that I was not netlisting to (It was an update of a previous design.) Check this: Make sure the LAYOUT you are trying to sync is the Board that you are importing your netlist to.
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