sorry andrew for the wrong word 'context sensitive menu' above, when i right click 'test or analysis name' in the data view assistant pane,context sensitive menu apperaed, but there is no customize menus at the end of the context sensitive menu and stimuli Regards
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Forum Post: RE: AMS Simulator in cadence virtuoso
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Forum Post: netlist generated by ADEXL doesn't match with ADEL
Hi, I am currently using Cadence IC6.1.6.500.4. performing corner simulation. All the corners have been good until I encountered a corner I didn't like, so I checked possible solutions with ADEL. The problem is that the result doesn't match with the one obtained with ADEXL. Obviously. I double checked all the settings, all the variables, the library path, the references to the schematic and they are exactly the same. So, I created the netlist using both ADEL and ADEXL and I compared them with a text comparator. Here attached there is the picture that shows the only difference encountered (left is ADEL netlist and right is the ADEXL). As can be seen, in ADEXL netlist the part I52.I74:2 is missing (in my case I52 and I74 are both instances, but I don't know what :2 means). Following this way, I tried to look at a transient signal in the part that is missing in the same corner, and ADEXL correctly plot it without any problems. I also tried to verify other corners, but in many other cases (I can't compare all the corners) the results from ADEXL perfectly match with the results of ADEL. even if the netlist difference is still present. I really don't know what's happening: furthermore, I don't know why when I open the ADEXL test I can't run a simulation with that interface (the picture is attached). I would be graceful to receive some help. Thank you and regards
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Forum Post: RE: Convert Altium Designer SchDoc to Capture CIS
Check to make sure that you have an ascii version of each of the different pages of the Altium schematic, you can also check the prjPCB file (open in a text editor) references all these different pages. If that doesn't help then you may need to send the ascii files and prjPCB file over to Cadence support / Channel Partner so they can look further.
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Forum Post: launch batch of sims with OCEAN
Dear all, I have a csv file with the test names and corner setup. format: test_name, Variable(s), corner example of the content AC Noise tt,passnom, 2.5V, etc ... Tran ... DC ... ..... then the full csv is imported into a list. Then, I would like to launch a Monte Carlo simulation per each entry in the list, for a specific test and corner not touching anything in the test (saved nodes, expressions, variables, etc) Thanks in advance. Best regards, Pedro
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Forum Post: measuring output transitions in ADE
Hi, I am running a simple transient simulation. During the simulation, I have three signals of interest: A is an input, B is an input, and C is an output. If A transitions when B is low, C should go high. I need to measure the total number of successful (and unsuccessful) transitions of C while it is subjected to local variations (e.g. Monte-Carlo 1000point run). I understand how to use "delay", etc. functions but this is really messy and I need lots of post-processing. Is Ocean the only way to determine these sort of logical expressions? Thanks,
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Forum Post: RE: Allegro screen white out
Hi again Phil, For me these white screens in Allegro only appears when Allegro window is maximized. But if you dont maximize it, and drag the boarders of Allegro window to the end of desktop instead, it wont show a white screen. Br Johan
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Forum Post: RE: Creating Oblong route keep out
Hi Bruekers, Sorry there are two typo in previous request, first one is if y1=y2 are equal co-oridnates and another one is FIRST_VIA = via1 from left hand side of midxy location and RIGHT_VIA=via2 from right side of midxy. Also how to reset the existing function, because the selected object(vias) is keep on alive and it is not end-of-function(eof). So again we need to hit the move or del tool tip for eof. Thanks! -Raj
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Forum Post: RE: Creating Oblong route keep out
Hi Bruekers, I found the function called axlClearSelSet() but i don't know how to use it for deselect the current objects when the target function has been done. Thanks! -Raj
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Forum Post: RE: Allegro screen white out
Please uninstall latest updates: support.microsoft.com/.../3205394 support.microsoft.com/.../3207752
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Forum Post: RE: measuring output transitions in ADE
Hi Matthew, it's not that hard to do. Do a "cross" function of your output (and maybe input too for comparison): ( I've done that in the CIW after the simulation) out=cross(i("/R0/PLUS" ?result "tran") 50u 1 "rising" t "time" ) (This is a current output of a resistor, finding the crossing of 50uA) "out" will now hold the waveform with the crossing points Now you just need to count the number of points: numEdge=drVectorLength(drGetWaveformXVec(out)) You probably could also use our "Eye Diagram Assistant" available in Viva and run all kind of statistics there. I'm not that familiar with it to explain it, but the documentation should be able to help. Regards, Marc
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Forum Post: RE: Allegro screen white out
WIndows 7 ?!?!
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Forum Post: RE: Allegro screen white out
Yes.
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Forum Post: RE: Allegro screen white out
Johan, that seems to correct the situation by not maximizing the Allegro window, thanks!!!
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Forum Post: RE: measuring output transitions in ADE
Nice ... I forgot about numEdge :) Yes it is a clean solution with cross. I will also check out the "eye diagram assistant". Thanks much!
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Forum Post: Understanding Innovus' hold analysis in a hierarchical design flow utilizing hard macros
Hello, I have got a problem with generating a hard macro and/or using this hard macro utilizing Cadence Innovus 15.2. The problem concerns the hold timing analysis of a top design which uses the previously generated hard macro. The following example depicts this issue and shows a hold analysis for one exemplary path. This path starts in the top design and ends within the hard macro. The hold analysis of the sub macro gives the following results: Other End Arrival Time 0.280 + Hold 0.030 + Phase Shift 0.000 - CPPR Adjustment 0.000 = Required Time 0.310 Arrival Time 0.315 Slack Time 0.005 The hold analysis of the top design gives the following results: Other End Arrival Time 0.353 + Hold -0.024 + Phase Shift 0.000 - CPPR Adjustment 0.000 = Required Time 0.328 Arrival Time 0.339 Slack Time 0.010 Both hold analysis are MET (for the tool). But I am not sure why the hold time for the pin of the sub macro is assumed to be -0.024 in the analysis of the top design. Related to hold analysis of the sub macro, the hold time for the pin should be -0.005 (what I think). The following picture gives an better overview of the delays for the path and the related clock within the different macro layers. So in my opinion the hold check fails here, because 0.654 - 0.633 = 0.021, which is smaller 0.030 (hold time of the register). This is what gatelevel simulation shows as well (hold violations). Both, hold analysis and export of the Liberty file for the macro is done in hold view. Here an extract of the significant innovus commands: Generate hold view: create_library_set -name best_library_set -timing "$MIN_TIMELIB" create_delay_corner -name dc_hold -library_set {best_library_set} create_analysis_view -name v_hold -constraint_mode {m_hold} -delay_corner {dc_hold} Do hold timing analysis: setAnalysisMode -analysisType onChipVariation -cppr both timeDesign -postRoute -hold -pathReports Export liberty file: set_analysis_view -setup v_hold -hold v_hold do_extract_model -lib_name sub_macro_hold -view v_hold sub_macro_hold.lib Afterwards the generated liberty file is added to MIN_TIMELIB for the run of the top design Any suggestions, what I am doing wrong?
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Forum Post: RE: netlist generated by ADEXL doesn't match with ADEL
Hi Marc, thank you for your reply. Actually I didn't know the troubleshoot function, it looks very useful and I will use it. My problem was that I set up manually the same conditions encountered in the corner that I didn't like in ADE, I simulated with ADEL and the result didn't match. So I decided to download again the test editor with the same ADEL I was using for the simulations, and then the result matched. Actually I don't really know the reason, because I thought that once you set the global variables in ADEXL, it should't make any difference the value of the so called Design Variables, so this is still not clear. I know that to use ADEL to verify a corner is not a good procedure, I think one should use directly the test editor, but in my case as you can see from the previous picture, I don't have the "run" option in the interface: is it only my problem or it depends on the Cadence version? Thank you and regards Nicola
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Forum Post: RE: Allegro screen white out
Are you sure? Look -> dl.dropboxusercontent.com/.../allegro.avi
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Forum Post: RE: test point spacing
I suggest that you contact your assembly vendor for their recommendations.
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Forum Post: RE: Allegro screen white out
I noticed that you have the infinite cursor. Try the following: Unset the infinite cursor - In the Display/cursor category of the User Preferneces set the pcb_cursor variable = cross Does that correct the screen? Set the variable infinite_cursor_bug_nt Does that correct the screen?
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Forum Post: RE: launch batch of sims with OCEAN
One approach would be to use ADE XL (or ADE Assembler) to do this. The corners UI already has an export and import CSV mechanism - it's not quite in the format you describe (particularly how tests are referenced), but I'm sure with a bit of munging you can get the CSV into the right format to import. Then you could run from ADE XL, or export an OCEAN XL script to do this - or using ADE Assembler in IC617, you could do a simple maeLoadSetup(lib cell view) and maeRun() script to batch run it. Regards, Andrew.
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