Not entirely sure you want to run this way (you can, but not sure why you want to do it), but the default changed in an IC616 ISR. You can do: envSetVal("adexl.testEditor" "showAllMenus" 'boolean t) This will add the run button in the ADE XL test editor; it's there anyway in later hot fixes. You can also use the Right Mouse->Debug environment over a failing corner to re-run in an ADE-L like environment the failing point. Regards, Andrew
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Forum Post: RE: netlist generated by ADEXL doesn't match with ADEL
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Forum Post: RE: netlist generated by ADEXL doesn't match with ADEL
Hi Andrew, thank you for your reply and for your help. Yeah, the way you indicate it's much better than modifying the test environment for every specific corner, so I'll follow your advice. Thank you and regards, Nicola
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Forum Post: RE: Allegro screen white out
It isn't a matter of setting, the problem occurs after the windows update
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Forum Post: RE: Simulation of standalone LNA IC
Why not just add a 1pF capacitor in the test bench?
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Forum Post: RE: How to create a polygon shape when it has the limition "dbCreatePolygon is not working for vertices greater than 4000" ?
Charley, You would have to break up the polygon yourself into smaller pieces. Whilst OA itself supports more than 4000 vertices (I'm not sure there's an actual limit) there are various limits in Virtuoso for historical reasons which still are 4000 (which used to be the limit in CDB). Regards, Andrew.
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Forum Post: RE: How can I simulate 'PLL Noise PSD' ?
You've posted on the end of a 3 year old thread which was talking about a capability which was end-of-life even then and has been removed from the tools. So that's why there's no help about the noise aware PLL flow. Essentially (as is covered elsewhere), the capability covered limited applications (only a limited number of PLL architectures), so we decided to drop it because to cover everything necessary was not really feasible. Regards, Andrew
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Forum Post: RE: PCell Instance inside PCell Callback Issues
You may be able to workaround this with this: unless(isCallable('aelSuffixNotation) procedure(aelSuffixNotation(num @optional _precision) let((numStr) numStr=case(type(num) ((string symbol) num) ((fixnum flonum) sprintf(nil "%N" num)) (t warn("argument must be a fixnum, flonum, or strnum") nil) ) when(numStr cdfFormatFloatString(numStr "auto") ) ) ) ) If this is defined in your libInit.il for your library, it would hopefully solve the problem. It provides an alternative (not identical) implementation of aelSuffixNotation (it ignores the precision) - but may be good enough for the callbacks to function correctly. Regards, Andrew.
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Forum Post: RE: Stacked Vias
Adi, The forum guidelines ask you not to post on the end of old threads - the thread you posted on was 7 years old... There is (in IC617 - at least in recent versions) viaGenerateViasAtPoint() which should (I think) be able to do this - note that the functions with a "via" prefix can't be used in PCells. Otherwise you'd have to create the vias using dbCreateVia() for each via in the stack. Regards, Andrew.
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Forum Post: Error SFE-23 (undefined model or subcircuit modp and modn) and Error (SFE-874)
Dear Cadence Community I've got some serious problems which i need to solve as soon as possible. I'm a new Cadence user, i've tried to launch ADE and unfortunately i can't make any simulations because of those problems below. Error found by spectre in `uklad', during circuit read-in. ERROR (SFE-23): "input.scs" 13: The instance `MP10' is referencing an undefined model or subcircuit, `modp'. Either include the file containing the definition of `modp', or define `modp' before running the simulation. ERROR (SFE-23): "input.scs" 29: The instance `MN11' is referencing an undefined model or subcircuit, `modn'. Either include the file containing the definition of `modn', or define `modn' before running the simulation. ERROR (SFE-23): "input.scs" 48: The instance `R0' is referencing an undefined model or subcircuit, `rpoly1'. Either include the file containing the definition of `rpoly1', or define `rpoly1' before running the simulation. When I tried to fix this problem this way Setup-->Model Library-->(added cds.lib) i've got another problem: ERROR (SFE-874): 14: Unexpected string value "#--------------------------------------------------------------------------------". ERROR (SFE-874): " 32: Unexpected end of line. ERROR (SFE-874): "33: Unexpected end of line. ERROR (SFE-874):34: Unexpected end of line. ERROR (SFE-874): 35: Unexpected end of line. ERROR (SFE-874):36: Unexpected end of line. ERROR (SFE-874): 37: Unexpected end of line. ERROR (SFE-874): 39: Unexpected end of line. ERROR (SFE-874): 40: Unexpected end of line. ERROR (SFE-874): "41: Unexpected end of line. ERROR (SFE-874): 42: Unexpected end of line. ERROR (SFE-874): "43: Unexpected end of line. ERROR (SFE-874): 44: Unexpected end of line. ERROR (SFE-874): 45: Unexpected end of line. ERROR (SFE-874): 46: Unexpected end of line. ERROR (SFE-874): " 47: Unexpected end of line. ERROR (SFE-874): 48: Unexpected end of line. ERROR (SFE-874): 49: Unexpected end of line. ERROR (SFE-874): " 50: Unexpected end of line. ERROR (SFE-874): 51: Unexpected end of line. ERROR (SFE-874): 52: Unexpected end of line. ERROR (SFE-874): 53: Unexpected end of line. ERROR (SFE-874): " 54: Unexpected end of line. ERROR (SFE-874): 55: Unexpected end of line. ERROR (SFE-874): 56: Unexpected end of line. ERROR (SFE-874): 57: Unexpected end of line. ERROR (SFE-874): 58: Unexpected end of line. ERROR (SFE-874): 59: Unexpected end of line. ERROR (SFE-874): 60:Unexpected end of line. Expected equals sign, numeric value or string value. (Deleted my path, just showing errors) I tried another way, adding file input.scs in the model library then the fatal error came out : FATAL (SFE-879): Recursive file include or library call: `/.../spectre/schematic/netlist/input.scs'. Can anyone help me with this issue please? Regards, Dominik
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Forum Post: RE: Error SFE-23 (undefined model or subcircuit modp and modn) and Error (SFE-874)
Hi Dominik, Oh dear - you really do appear to be trying random things which will stand no chance of working. Often design kits will set up the model path automatically to ensure the models are defined - if they don't, there's presumably some documentation with the design kit to tell you where the model files are. These are the transistor models (subckts, model statements) that need to be included so that Spectre knows the meaning of the primitive devices (modp and modn in your case). These are probably defined somewhere in a file with a ".scs" suffix (although it is possible that they're defined in SPICE syntax so they could be described differently). Without knowing what technology or design kit you're using, I doubt anyone could guess what the file is likely to be called (unless they happen to recognise the "modn" and "modp" model names). Including the cds.lib makes no sense; that's the definition of Virtuoso libraries (containing symbols, schematics, CDF, layouts and so on) for the Virtuoso tools to use. Virtuoso must be seeing that otherwise you couldn't draw your schematics. It's certainly not a spectre model file, hence the syntax errors. Including the input.scs similarly makes no sense - all the model libraries form does is specify a bunch of files to include in the input.scs that it is generating, so putting a reference to itself makes no sense (hence the error about it being recursive). Regards, Andrew.
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Forum Post: RE: Error SFE-23 (undefined model or subcircuit modp and modn) and Error (SFE-874)
Hi Andrew Thanks for the quick answer, I presume that the only thing I need to do is to add the right file with models ? Hit-KIt: ams_4.10 Tech:c35b4 Regards, Dominik
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Forum Post: RE: how to add lvsIgnore property to a cell made by myself.
OK, I didn't realise you were doing it on a hierarchical component rather than a leaf cell. If you do that, it omits the instance line, but still netlists the underlying schematic as a .subckt - it just wouldn't be referenced. If you don't want it to appear at all, what I'd suggest is going to the library manager, and copying the symbol view for the block you wish to ignore to be called "auCdl", and then open the auCdl view for edit, and add a cellView property (Edit->Properties->CellView in the symbol editor) and then adding a boolean property called "lvsIgnore" with value t. Then the instance and the definition won't appear. Regards, Andrew.
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Forum Post: RE: Error SFE-23 (undefined model or subcircuit modp and modn) and Error (SFE-874)
Hi Dominik, I think (I haven't used an AMS hit kit for a few years) that you have to include /spectre/h35/cmos35.scs (it might be h35, or s35, or c35), and you'd need to specify an appropriate section from the models. However, the section names you should use may depend on the technology, version and so on - and you probably also want other model files included. I strongly suggest you contact AMS to ask them if you don't have the documentation, since I would hate for you to be including the wrong files and getting incorrect simulation results. Regards, Andrew.
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Forum Post: RE: Error SFE-23 (undefined model or subcircuit modp and modn) and Error (SFE-874)
Hi Andrew, I'll try to do so, Thanks for help and advice. Regards, Dominik
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Forum Post: RE: Import physical view doesn't include all pins.
My understanding (without doing experiments to prove this) is that load physical view will only copy pins across if the nets/terminals are in the target view (i.e. the source schematic view had terminals with those names). It doesn't copy pins that weren't in the source schematic, because otherwise you would have a mismatch with the source view. Might that be what you're seeing? Otherwise, I think you'll have to supply more info (you didn't even mention which version you're using), and it's probably going to be easier to answer this with sight of your data (so customer support is probably the best option). Regards, Andrew.
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Forum Post: RE: AMS Simulator in cadence virtuoso
To answer (rather belatedly) your original question about saving the internal variables, bring up the test editor (double click on the test name in ADE XL) and then Outputs->Save All and set the "Save AHDL variables" to "all". You can do it more selectively, but you either need to add a probe tcl command or do this from within the SimVision debugger - so it keep it simple, you can get all of the internal variables this way. After simulation, you can use the results browser to access the internal signals. I've no idea what your last two questions are trying to ask. If you were (via some roundabout way) asking about using Setup->Stimuli when using AMS as the simulator - the simple answer is that it doesn't exist. This is only there for spectre. Regards, Andrew.
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Forum Post: RE: Accessing ADEXL outputs from Ocean
Eric, This is much harder than it should be (I think an enhancement in this area would be worthwhile). The RDB doesn't contain the waveform data, so the value slot for something with a waveform will just say "wave". You'd need to do something like: axlSess=axlGetWindowSession() sevSess=axlGetToolSession(axlSess " testName ") ; possibly need the ?history here too asiSess=sevEnvironment(sevSess) ; find the output structure you want output=car(exists(output asiGetOutputList(asiSess) output~>name==" OUTNAME ")) Then output~>expression will contain the expression you want. Then you could use (say) the rdb->test("testName" "C0_0" 1) function to get the info about a particular corner and point number, and from this you have ~>resultsDir - so I can do: result=rdb~>test("testName" "C0_0" 1) openResults(result~>resultsDir) waveform=eval(output~>expression) plot(waveform) The new Maestro API for ADE Explorer and Assembler also doesn't quite handle this - the maeGetOutputValue() function also returns "wave" for something that is a waveform. Regards, Andrew.
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Forum Post: RE: No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic
Maybe you've not compiled your connect modules and connect rules? Also, you might find it easier using irun rather than the three-step (ncvog/ncelab/ncsim approach). I suggest you contact customer support - this will be much easier to figure out if we can see your data. Regards, Andrew
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Forum Post: RE: PVS-QRC flow and QRC_Advanced_Modeling licence
Search in the QRC documentation for "Advanced Modeling" and you'll find there are a few features needed for modeling technologies 32nm and below that require the QRCX320 Cadence Quantus QRC Advanced Modeling GXL Option license. That's what the first issue is complaining about. The second (and third) doesn't really have enough information to go on - I suggest you contact customer support (hopefully you'll have done that by now anyway). Regards, Andrew.
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Forum Post: RE: I installed a new GF55lpx PDK, and I when I run PVS-QRC, I get incorrect models name in Spectre netlist and in av_extracted view
Steve, Most likely this is because you have the settings on the Netlisting tab of QRC incorrectly set. If you have them set to "Include Model" for the two parasitic entries, it will end up adding a model parameter on each parasitic in the extracted view (which will then get netlisted by the spectre netlister, for example) which gives an indication of which type of parasitic it is. Most of the time, you probably don't want that and so should have it set as follows: Regards, Andrew
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