To be honest, there's not enough information to go on. I would suggest you contact customer support (I would hope you've resolved it after 2 months; I was just revisiting my inbox for things I'd not had a chance to follow up on). Andrew.
↧
Forum Post: RE: LVS error
↧
Forum Post: RE: ADE Explorer switch view list
Eduard, I would suggest you contact customer support . I'm not sure what the issue is here from the description you've provided (even with the version number, nothing jumps out). Andrew.
↧
↧
Forum Post: RE: Stability factor of differential LNA
Hello Mr Andrew, Any update on this matter? I would really appreciate any tips or tricks to test stability with VCVS as the buffers are decreasing my gain a lot and the CG gain with buffers is 4dB down from 12dB. Regards, Qusai
↧
Forum Post: RE: Stability factor of differential LNA
Qusai, No, as I said in my earlier reply , I can't really help with this. To be honest, I can't really see how Kf would work with a vcvs used (and I'm not sure how that helps in a real circuit anyway). Andrew.
↧
Forum Post: RE: Transient Violations taking too much disk space
Hi Andrew, Many thanks. Yes the checklimitdest was set to psf. Changing this and the dochecklimit has reduced the disk space from over 70GB to under 100MB! Simulation time was also significantly reduced. For completeness, the spectre version information is below: Spectre (R) Circuit Simulator Version 18.1.0.335.isr6 64bit -- 19 Apr 2019 Best Regards, Chris.
↧
↧
Forum Post: RE: xnets
You can add a Comps level property (Edit - Object Properties then Comps in the Find pane) called NO_XNET_CONNECTION with a value of True which stops the xnet being created. This can also be added in the schematic.
↧
Forum Post: how to setup customized rules file to simulation a circuit with 2 level of voltage 1.8v and 3.3v ?
Hi All, I am using using cadence 5.1 and AMS embedded to in it. I saw that we have a connection rule which interpreted the analog to digital waveform but it only realize 1.8v. How can I change it to make it work with correct voltage level for 3.3v ? currently all will be just logic "1' . Please help thanks Nhumai
↧
Forum Post: RE: xnets
Steve, assuming no constraints in the schematic are to be transferred to the PCB, could checking the "ignore electrical constraints" box in the setup for exporting a netlist be an easy option? We setup constraints at the board level and if we don't check the box our board level constraints get hosed.
↧
Forum Post: RE: Import gerbers from Altium to PCB Editor 16.6
ok thanks
↧
↧
Forum Post: Innovus Stylus Common UI
How can I make innovus start with common UI instead of legacy? When I launch Innovus with command "innovus", I get the legacy UI. I have Innovus version 17.11 installed. Thanks in advance.
↧
Forum Post: RE: Stability factor of differential LNA
Dear Qusai, I was not aware of your post until I read Andrews response to your request for additional thoughts. I would have added my comments earlier - sorry! The methodology you are using to establish absolute stability appears to differ from the methodology I believe most LNA designers use. Typically, after the optimum match (which may not be perfect) to your source impedance has been determined, the impact of load impedance is considered in light of the stability. Using an ideal vcvs as the load seems totally unrealistic as a load as you can never realize it. If your load is known, that load is used to assess stability. If not, one determines the stability as a function of the range of expected possible load impedance. The load impedance will clearly impact gain of the LNA, so if a specific gain is required, this will limit the possible load impedances. In summary, finding the stability using an ideal vcvs load impedance is not really a relevant measure of stability. If it is useful, a presentation made by Avago on a similar topic might be useful at URL: www.ntms.org/.../MUD_W5LUA_LNAs_Web.pdf I hope, Qusai, I understood your question correctly...and my thoughts help a little. Shawn
↧
Forum Post: noise/jitter transfer function along clock-driven inverter chain
Hi everyone, hope the section is correct. I'm simulating with spectre the inverter chain shown in the figure below where the input signal is a 30GHz sinusoid that is AC coupled to first inverter. My goal is to investigate its noise. x6, x12... is the multiplicity of the inverters. What I want to do is to check how the noise coming from the fiirst inverter only is propagated along the chain and transformed into jitter on node N1 to node N4. To furthermore simplify I went to Simulation -> Options -> Analog and I checked "Noise Contribution" to On, specifying the first inverter only as noise contributor (thermal). I set up the PSS simulation with Beat Frequency 30GHz and 10 harmonics. **netlist** pss pss fund=30G harms=10 errpreset=conservative autosteady=yes + annotate=status Then the pnoise: since it is a periodic simulation, it's sufficient to check the noise up to half the PSS Beat Frequency. Output Freq Range is absolute and set to 10k to 15G, as seen in the picture. At every node, there will be the folding of every noise bandwidth around the harmonics of the PSS toward the 10k-15G bandwidth. But I want to simplify even more, choosing Sidebands 15G-30G and 30G-45G only in the pnoise Sidebands form. This is to check how the noise placed around the 30GHz harmonic only contributes to noise. Finally, since it's a jitter simulation, I set "Noise Type" to "sampled(jitter)", "Timing Event" to "Edge Crossing" and set a measure for each transition of N1-N4 nodes using as trigger the same measured signal (e.g. measure N1 has the same N1 signal as trigger). **netlist** pnoise pnoise start=10k stop=15G dec=5 sidebands=[-1 1] noisetype=sampled \ sampleratio=1 measurement=[pm0 pm1 pm2 pm3] annotate=status pm0 jitterevent trigger=[N4 0] triggerthresh=0.45 \ triggerdir=rise target=[N4 0] pm1 jitterevent trigger=[N3 0] triggerthresh=0.45 \ triggerdir=rise target=[N3 0] pm2 jitterevent trigger=[N2 0] triggerthresh=0.45 \ triggerdir=rise target=[N2 0] pm3 jitterevent trigger=[N1 0] triggerthresh=0.45 \ triggerdir=rise target=[N1 0] What I get from the results are the following time waveforms (N1 red... N4 green). Then if I calculate the Jee integrated from 10k to 15G I see that is always increasing along the chain from 42f to 47f. However, if instead of Jee I plot the Output Noise spectrum I get the following behavior, with the same Node-Color relation as before: N4 output noise is lower than the N3 output noise! How is that possible? So here's my questions: 1) how is that possible that noise is decreasing along the chain? 2) I'd like to plot the noise transfer functions along the chain: for example, how the noise in N1 in the bandwidth 15G-30G is going to N4 noise bandwidth 0-15G. What is the best way to have such a transfer function? I tried to use the PAC sampled and also the PXF sampled, but I am not sure how to combine the results to get the sort of "flat gain" that I see in the noise spectrums above, e.g the 53.5/35.3 ~ 1.52 "voltage gain" between N1 and N4. Thank you in advance. Nicola
↧
Forum Post: RE: Copy synchronous clones between layout views
Much appreciate it, Andrew! The above forwarded post indeed helps simplify my workaround scripts. Cheers, Duo
↧
↧
Forum Post: RE: noise/jitter transfer function along clock-driven inverter chain
Dear Nicola, [quote userid="460645" url="~/cadence_technology_forums/f/custom-ic-design/43477/noise-jitter-transfer-function-along-clock-driven-inverter-chain"]So here's my questions: 1) how is that possible that noise is decreasing along the chain?[/quote] I have experienced the similar non-intuitive results using a pss/pnoise (sampled jitter) analysis of a number of circuit topologies very similar to the schematic you describe. I have opened a case with Cadence to better understand the non-intuitive results and am currently working with one of their very best Application Engineers to resolve the issue - or at least understand my incorrect use of the new tool! Shawn
↧
Forum Post: Equivalent skill for Create Detail
Hi Guys, Anyone know equivalent skill for create detail. Eugene
↧
Forum Post: RE: noise/jitter transfer function along clock-driven inverter chain
I too would suggest opening a case with customer support . My guess is that what you're seeing is related to the different edge speeds at the different nodes, but it's quite hard to tell from just pictures - I would want to look more closely at the data. Regards, Andrew.
↧
Forum Post: Incisive Metrics Center User Guide
Hi Team, I would like to download "Incisive Metrics Center User Guide", I could not find in the cadence/support/manuals. Can you please provide me the link or path to download the same ? I am doing functional coverage with IMC. Thank You, Mahesh
↧
↧
Forum Post: RE: Libraries not imported in the Library manager
Thanks very much. We will check again and contact the support. I have another question about this library. When we used this library(cmos045) in Cadence 615 and 616, it worked well. But recently we tried to implement the library in the same way in Cadence IC6.1.7-64b.500.21. There are several problems. The installation goes well, but the simulation has encountered proble. The details are as follows: In the « .simrc » file, the switchviewlist and stopviewlist are defined as follows : ;;;;;; UNICAD update of .simrc begin ;;;;;; UkerSimrc = t loadi(strcat(getShellEnvVar("UNICAD_KERNEL_ROOT") "/Uker.ile")) UkerSimrc = nil ;;;;;; UNICAD update of .simrc end ;;;;;; loadi( strcat(getShellEnvVar("PDKITROOT") "/" "PDK_STM_cmos040lp_AMS_7m4x0y2z_2V51V8.simrc")) asiSetEnvOptionVal(asiGetTool('spectre) "switchViewList" list("SimMosfetStandard" "SimDiodeStandard" "SimCpolyStandard" "SimCmetalStandard" "SimCfringeStandard" "SimCfringeAccurate" "SimResistorStandard" "SimResistorAccurate" "SimResistorHF" "SimResistorHFV" "SimBipolarStandard" "SimCmimStandard" "SimCapaStd" "SimCapaAcc" "SimMosfetAccurate" "SimMosfetrfStandard" "SimMosfetrfPSP" "SimInductorStandard" "SimInductorAccurate" "SimVaractorStandard" "SimCmomStandard" "SimCmomAccurate" "hspiceS" "hspiceD" "auCmos_sch" "cmos_sch" "cmos.sch" "ads_schematic" "schematic" "auGate_sch" "auGate.sch" "gate_sch" "gate.sch" "extracted" )) asiSetEnvOptionVal(asiGetTool('spectre) "stopViewList" list("SimMosfetStandard" "SimDiodeStandard" "SimCpolyStandard" "SimCmetalStandard" "SimCfringeStandard" "SimCfringeAccurate" "SimResistorStandard" "SimResistorAccurate" "SimResistorHF" "SimResistorHFV" "SimBipolarStandard" "SimCmimStandard" "SimCapaStd" "SimCapaAcc" "SimMosfetAccurate" "SimMosfetrfStandard" "SimMosfetrfPSP" "SimInductorStandard" "SimInductorAccurate" "SimVaractorStandard" "SimCmomStandard" "SimCmomAccurate" "hspiceS" "hspiceD" )) asiSetEnvOptionVal(asiGetTool('spectre) "modelFiles" list( strcat(getShellEnvVar("PDKITROOT") "/" "/SIMU/SPECTRE/ST/corners.scs" ) But when we perform a simulation, the two lists in the environment settings appear like : spectre cmos_sch cmos.sch schematic veriloga spectre When we run the simulation, the error in the CIW is : ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the instance 'M0' in cell 'inverter'. Add one of these views to the cell 'nlvtlp' in the library 'cmos045', or modify the view list so that it contains an existing view. When 'SimMosfetStandard' is added into the switchviewlist, there is no output, and the warnings in “spetre.out” file are: Warning from spectre during AHDL read-in. WARNING (VACOMP-2435): The environment variable CDS_AHDLCMI_ENABLE is no longer supported. Therefore, the simulator will use the default compiled C code flow. Warning from spectre during hierarchy flattening. WARNING (SPECTRE-17101): The value 'psf' specified using the 'checklimitdest' option will no longer be supported in future releases. The warnings in CIW are: WARNING (OSSHNL-117): Ignoring switch view 'SimMosfetStandard' of cell 'nlvtlp' in library 'cmos045', as it does not contain any instance. To netlist this cell, add this switch view to the stop list or to ignore any specific instance set the property 'nlAction' to value "ignore" on this cell view. WARNING (OSSHNL-117): Ignoring switch view 'SimMosfetStandard' of cell 'plvtlp' in library 'cmos045', as it does not contain any instance. To netlist this cell, add this switch view to the stop list or to ignore any specific instance set the property 'nlAction' to value "ignore" on this cell view. When the switch lists and stop lists in the « .simrc » file are injected by hands, the errors appear like : Netlist Error: Could not find netlist procedure:UartDirectSubcktCall instance "M0" in cell-view "Test" "inverter" "schematic" Netlist Error: Could not find netlist procedure:UartDirectSubcktCall instance "M1" in cell-view "Test" "inverter" "schematic" So, in your opinion, is it possible that the Cadence 617 does not support this library? Thanks very much in advance. Best regards, UU
↧
Forum Post: dbLayerAnd() function is not working
Dear all, I need your help on. Below is my code: procedure( checkNoShapeOutsideTheBoundary() cv = dbOpenCellViewByType("testnew" "abc" "layout" "maskLayout" "r") prBoundary = '( ((0.0 0.0) (0.03 0.01725)) ) shape_location = '( ((0.016 0.012) (0.0175 0.0125)) ) results = dbLayerAnd(cv "M1" shape_location prBoundary) println(results) );procedure ***prBoundary: PrBoundary layer ***shape_location: M1 layer But return the results: nil Is there something wrong with my code? Please help to clarify. Thank you. Best Regards, Phuong Truong
↧
Forum Post: RE: noise/jitter transfer function along clock-driven inverter chain
Hi Sawn, hi Andrew, thank you for your answers. I'll go through the local customer support. Yes, Andrew, my guess is the same: the simulator is calculating the jitter, but then to extrapolate the output noise at each node takes the slope into account. In fact, i checked that the ratio between the rising slopes at N3 and N4 and the low-frequency output noise at the same nodes: it's the same. This stated, I'm not sure I'll be able, in a simulation with all contributors and sidebands, to extract the correct contributors to jitter at the output of a chain since I usually calculate them through the noise summary, that is equal to the incorrect Ouput Noise spectrum that I plotted above. Shawn, please let me know if you have updates on your side! Thank you Nicola
↧