Hi! I'm trying to design buffer amp for specific application, so I want to check stability such as phase margin using an instance 'iprobe'(actually it doesn't matter to use ac simulation). However, the loop gain phase plot of the circuit starts with 0 instead of 180 deg and it's unexpected plot. I think it could be related with positive feedback or multi loops, but I'm not sure about it. The transient result of the circuit works well, but I want to check the figure of phase. Could you please help me? How can I make it clear? Thanks.
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Forum Post: Stability check issue during phase starting with 0 degree
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Forum Post: RE: xnets
So once you have invoked Constraint Manager at the front end (from Capture) the design get locked in a Constraint Flow and to avoid the issues you are seeing you MUST back annotate the board to the schematic which will transfer all the constraints from PCB to schematic. This does work very well.
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Forum Post: RE: Equivalent skill for Create Detail
Maybe you look for axlDetailSave and axlDetailLoad? Bram
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Forum Post: RE: Incisive Metrics Center User Guide
All the product manuals are available in their respective tools via the "cdnshelp" command, but you can also get them here: https://support.cadence.com/apex/ProductManuals . A direct link to the latest IMC docs: Integrated Metrics Center User Guide 19.09
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Forum Post: RE: Running xrun command in vsif file
When you say there is a "prompt change", I guess you mean the working directory change, right? This is by design; vManager creates a unique working directory for each test so that they can run in parallel without all trying to write to the same log files etc. You script needs to point to the full path where the files are located. There are many ways to do this, perhaps the easiest, if your source files are in the same directory where you started vmanager, is to use the syntax $ENV(PWD) to point to vManager's working directory. group basic { test test { run_script: xrun -quiet -timescale 1ns/1ns -access +rw $ENV(PWD)/memory_tb.v $ENV(PWD)/mem_tb_top.e $ENV(PWD)/test_write_read_all.e ; }; }; There are other ways to do it, e.g. for the e files you can setenv SPECMAN_PATH before launching vManager, and ensure that SPECMAN_PATH points to all the directories where your e files are located. This doesn't work for Verilog or VHDL though. By the way, I've cleaned up your quotes as your original command had them where they were not required, and I propose you remove the -unbuffered as it hurts performance.
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Forum Post: RE: Stability check issue during phase starting with 0 degree
You are giving very little detail, so it's hard to guess the cause for this behavior in your case. A plot of the loop gain results and the schematics would certainly help. You can take a look at https://designers-guide.org/forum/YaBB.pl?num=1294178255 ; this thread covers one possible reason for such a behavior.
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Forum Post: RE: Stability check issue during phase starting with 0 degree
Thank you for your answer. Actually I think it's similar with my case, but I can't find vprobe in cadence. Then it's only one way to check the stability is using Nyquist stability criterion, if I want to know specific figure of phase margin? Is it right?
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Forum Post: RE: use of skill function "vhdlimport"
Hi Andrew, Could you please suggest if there is any skill command to import system verilog ? When I use "schInstallHDL" to import a systemverilog file, it gives extraction error. I can go for "cdsTextTo5x", but it gives me error to because of some new command in systemverilog that doesn't support with "cdsTextTo5x". Could you please suggest ? Thanks & Regards, Amar
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Forum Post: RE: Stability check issue during phase starting with 0 degree
In my example circuit, Vprobe is an ideal voltage source with 0 V that is used as the probe in the stb analysis. You can also use a current probe (iprobe) for this purpose. If your results look like the ones in my example, you can probably simply ignore the behavior of the loop gain at low frequencies and calculate the phase margin in the usual way after cutting off the low-frequency results.
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Forum Post: RE: Running xrun command in vsif file
Hi Stephen, Thank you for tour reply, it works perfectly. It seems that my file's path was wrongly defined. Best regards. Yohan
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Forum Post: RE: noise/jitter transfer function along clock-driven inverter chain
Of course the sampled noise can decrease along the chain if the signal slope increases. There isn't anything strange about this as long as the resulting jitter does not decrease. The output noise is not "incorrect" because of this and the noise summary of the sampled noise correctly shows the devices that contribute to the jitter. Sidebands don't make much sense in a sampled pnoise analysis; they simply give you a shifted version of the original result at sideband 0 (and in that result, the noise at 15G-30G is just a mirror image of the noise at 0-15G). Sampled PXF or sampled PAC is the right way to examine the transfer functions. You can also try the parameter separatenoise=yes (I have never really used it), but this won't work if you also use pnoisemethod=fullspectrum.
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Forum Post: RE: dbLayerAnd() function is not working
Hi Phuong, It fails because dbLayerAnd does not work with lists of bBox descriptions. It works with lists of database objects for the shapes you want to do the And operation and generations the new shapes in the cellView. Instead you should use dbPointArrayAnd, but this expects lists of lists of points (each list of points is the points in a polygon, so not just two points for a rectangle). You could do something like this: procedure(CCFbBoxToPolygon(bBox) destructuringBind(((llx lly) (urx ury)) bBox list(llx:lly llx:ury urx:ury urx:lly) ) ) result=dbPointArrayAnd(cv mapcar('CCFbBoxToPolygon shape_location) mapcar('CCFbBoxToPolygon prBoundary)) By the way, if you were expecting your code to create a shape on M1, you probably should have opened the cellView in "a" mode (it would create the shapes, but it won't be saveable if you open in readonly mode) Regards, Andrew.
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Forum Post: RE: Extract logic cells from design to match cells provided by pdk?
Using Altera FPGAs instead of conventional standard cell ASICs, you can conceivably decrease the complex nature of the structure procedure and fundamentally reduce cost. Read more about FPGA and conventional standard cell ASIC gadgets at custom writing .
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Forum Post: RE: use of skill function "vhdlimport"
I don't believe there's a SKILL function to do the import, but cdsTextTo5x should work. Did you use the -LANG systemverilog argument when you used cdsTextTo5x? If so, what was the error? Andrew.
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Forum Post: RE: use of skill function "vhdlimport"
Hi Andrew, Thanks for your reply. Yes, I used -LANG as systemverilog. Below is the error it shows. I am using below. cdsTextTo5x -CDSLIB ./cds.lib -LANG systemverilog -LIB myLib -CELL myCell -VIEW functional -SYMBOL symbol verilog.sv => ERROR (SHDB-11): Failed to parse the verilog module for design unit (myLib myCell functional). Either there are compilation errors or cellview is not writable or verilog module does not exist in the file. ERROR (TI-7001): Cannot load the connectivity information for cellview 'myLib/myCell/functional' in text file 'verilog.sv'. I feel like, its a compiler error. But it doesn't print the exact error line. Is there any other way to import the systemverilog I can try? Regards, Amar
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Forum Post: RE: use of skill function "vhdlimport"
Hi Amar, I suggest you add -LOG problem.log to the command line and then that log file should contain details of what the issue is. It's likely that any other way of importing the file (such as creating the view in Virtuoso and pasting the text in) would lead to the same problem. Andrew.
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Forum Post: RE: Adding Terminal and Pins In Pcell Using Pcell Designer Tool.
Hi Andrew, Thank you for your reply. I have one more query regarding terminals. When i copy a shape which has terminal on it using "copy" command , the terminal is getting copied. But when i use "array" command, the terminal connectivity is lost in the resulting array. Can you tell me why this is happening and is there any alternative way to retain connectivity? 1. Using Copy command 2. Using Array Command
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Forum Post: RE: use of skill function "vhdlimport"
Hi Andrew, The log file prints the details of the error. Looks like the verilog is using some package that is not found, though I have defined the packages. I will check on this. Thank you, it helped to move forward. Regards, Amar
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Forum Post: RE: Libraries not imported in the Library manager
This is very specific to the UNICAD (ST) environment. You would be better off contacting ST Microelectronics for support, since it's their design kit and design environment that is involved here (I can't comment on whether there's anything in that environment that is overriding the switch view lists etc, or why the netlist procedure is not loaded). Regards, Andrew.
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Forum Post: RE: Adding Terminal and Pins In Pcell Using Pcell Designer Tool.
The array command is not designed to retain connectivity - it's for doing a simple "fill" type operation but driven by the number of rows and columns (for example). It can place mosaics or stepped arrays of shapes. We decided not to overcomplicate it by adding connectivity support as well, as the copy command (either in a loop, or with the repeat parameter) can be used to achieve this with control of the connectivity. Regards, Andrew.
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