Dear All, We are able to find the Cgg,Cgs, Cgd and other junction capacitance of the MOS in ADE. Is there any way we can find the Gate Resistance of MOSFET in spectre-ADE ? Kind Regards,
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Forum Post: Finding Gate Resistance of MOSFET in spectre-ADE.
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Forum Post: Concentric Pads
Hi everybody, I am currently trying to create a proper footprint for a screw-on Type K connector [ datasheet ]. In essence it comprises two pads: a small one for the signal in the middle, surrounded by a bigger, donut-shaped one for ground (plus two screw terminals which are of no importance to this question). When I place these two pads in the footprint, I get a DRC error saying that these pads overlap event though the air gap between the pads is actually big enough. Is there a way to get this 'right', i.e. without creating DRC errors? And is there a clean way to add some (say 5 or 6) top-to-bottom vias along the ground donut?
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Forum Post: phase noise/vin vs. frequency
Hi all, I have a Phase Interpolator to simulate in Periodic Steady-State (shooting). This circuit synthesizes a clock with digitally-controlled delay on its ouput based on input reference clocks. I would like to simulate the output phase noise / input phase noise transfer function (this could be either the input reference clock or VDD for PSRR) in a Bode diagram (over frequency); could somebody explain to me the way to do that ? I I know how to do for a voltage output / voltage input transfer function using PXF analysis, or simulating the intrinsic phase noise using PNOISE, but not for outpout phase noise / input phase noise transfer function... Thanks a lot in advance. PS: I am using Spectre with ADE-XL.
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Forum Post: RE: Finding Gate Resistance of MOSFET in spectre-ADE.
This will depend on the model used. For bsim4 I see there's 59 rgbd (Ohm) Gate bias-dependent resistance. (see "spectre -h bsim4" and search for "Operating Point"). Andrew.
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Forum Post: Does MC mismatch simulation reflect best or arbitrary layout ?
Hi, one question regarding MonteCarlo (MC) mismatch simulations is, how the simulation results are related to layout. Does the mismatch simulation reflect the case where the layout is optimized regarding mismatch (e.g. best common centroid layout approach + dummies) ? In this case, a non-optimum layout would cause more/bigger mismatch than simulated. Or does the mismatch simulation reflect the case of arbitrary placed components all over the wafer (or over a certain layout area)? In this case, an optimized layout (centroid + dummies, etc.) would cause less mismatch than simulated. For example, if one designs a R2R-DAC and the mismatch-simulation shows that all specifications are fulfilled. Would a straight forward compact layout (with dummies etc.) be good enough - or does only a best-optimized common centroid layout guarantee these results ? BR HoWei
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Forum Post: RE: Does MC mismatch simulation reflect best or arbitrary layout ?
Mismatch simulation actually draws no conclusion about the quality of the layout - what you are simulating is not the systematic mismatch due to poor alignment, but the residual random variation of each local device. So put another way, the models are not trying to model the effects caused by good/bad layout. There may then be additional mismatch caused by bad layout, but that's not what you're simulating. If that was what was going to be simulated, the foundries would have to characterise this somehow and then there would need to be a tool which tried to assess correlation based on layout position - there are no models and no tool to do that though. There are some LDE (layout dependent effects) analysis tools which can look at the layout environment and use that to capture the change in behaviour of devices due to their environment, but that's not quite what you're asking here. That said, running Monte Carlo with mismatch does tend (particularly if you use mismatch contribution) to give you a feel for the variability of which devices leads to the biggest variation of your output measurements which could help you assess which devices require the most care about placement. Andrew.
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Forum Post: RE: Does MC mismatch simulation reflect best or arbitrary layout ?
Hmmm, I understand that that the simulator cannot draw any conclusion on the quality of the layout. Basically you are saying that some effects (LDE: poly/doping/other gradients along the wafer) are not included in the mismatch simulation - and a care must be taken in layout to compensate these (unmodeled) effects ? This actually tells me, that it is always worth to do best common centroid for matching devices, because additional effect will come on top of the mismatch parameter variattion. Just after posting this question I found the relevant chapter in the DRM that states: "the mismatch model includes the analysis of identical devices IN CLOSE PROXIMITY". That tells me that the mismatch (and thus the measured results) can be worse if I do not take care about proper layout (centroid), dummies, etc. Did this summary match what you wrote ?
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Forum Post: RE: Does MC mismatch simulation reflect best or arbitrary layout ?
Effectively, yes. You can model some of the LDE effects by extracting relevant parameters (e.g. LOD, stress parameters such as SA, SB etc, well proximity effects) but this is not really anything to do with the mismatch simulation. The foundry document you found is effectively saying the same thing - that the model is just capturing the remaining variation (the random part) after good layout practice has been taken into account (that variation would be systematic). So yes, what you're saying is effective the same as what I'm saying. Andrew.
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Forum Post: RE: Does MC mismatch simulation reflect best or arbitrary layout ?
Perfect ! Thanks once again !
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Forum Post: How to properly shutdown virtuoso?
I mean the cds.log, virtuoso.conf, simulstion, and everything. Cdsnameserver, clsbd process, etc.
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Forum Post: RE: noise/jitter transfer function along clock-driven inverter chain
Hi Frank, [quote userid="4061" url="~/cadence_technology_forums/f/custom-ic-design/43477/noise-jitter-transfer-function-along-clock-driven-inverter-chain/1365426#1365426"]Of course the sampled noise can decrease along the chain if the signal slope increases. [/quote] to avoid any doubt I did the following simulation. I created an ideal inverter using the switch element from analogLib that gives a very steep response and I checked what happened at its output. The slope is then largely increased from N4 to this new output, but the noise is not decreasing, but largely increasing. In this very simplified situation, since noise contributor is only the input inverter, the jitter must be constant after the first inverter. In other words, the ratio between integrated noise over slope must be constant. When the ideal inverter is introduced, since the slope tends to infinity, the noise too must go to infinity to keep the ratio (i.e. the jitter) a constant. [quote userid="4061" url="~/cadence_technology_forums/f/custom-ic-design/43477/noise-jitter-transfer-function-along-clock-driven-inverter-chain/1365426#1365426"]Sidebands don't make much sense in a sampled pnoise analysis; they simply give you a shifted version of the original result at sideband 0 (and in that result, the noise at 15G-30G is just a mirror image of the noise at 0-15G).[/quote] I agree that noise seen at the output node at every other bandwidths like 15-30, 30-45, 45-60 etc... will be the same as the one you get in 0-15G. However, the number of sidebands that we are talking about are the folded ones, that you can choose in the pnoise form. Every high-frequency bandwidth will contribute to the 0-15G bandwidth noise. In this simplified simulation I chose to keep 2 bandwidths only contributing to the ouput noise.
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Forum Post: Save VHDL variables of specific hierachy
Hello, I'd like to save all VHDL variables in ADE Assembler of a VHDL file in an transient AMS simulation. The VHDL file is referenced inside a verilogams wrapper and marked as "External HDL" in the config view of the testbench. How is it possible to save all variables in this specific subcircuit / VHDL file? When I save all nets (Outputs -> save all... -> Save nets -> all), the variables are saved. However, this saves also all analog nets, which results in a huge simulation result and is not an option.
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Forum Post: RE: xnets
Steve, you are correct. I invoked the constraint manager in Capture (even tho I didn't use it) and then I started getting the xnets. I add the property NO_XNET_CONNECTION and now the xnets are gone. How did you find out about adding the property? Sucks that Allegro forces me into a different flow without asking/warning that it's happening. Thanks for the help. Phil
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Forum Post: RE: Save VHDL variables of specific hierachy
You would use the probe tcl file on Simulation->Options->AMS Simulator, Miscellaneous tab. If you use the interactive debugger (simVision) you can create probes interactively and then see the corresponding probe tcl command - so you can use appropriate scoping and so on to create probes for what you want. Regards, Andrew.
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Forum Post: RE: How to properly shutdown virtuoso?
You properly shut it down using File->Exit (or typing exit() in the CIW). The cdsNameServer, clsbd are actually daemon processes that are shared amongst multiple Virtuoso sessions (and for tools beyond Virtuoso); they are started automatically the first time that Virtuoso launches and persist (intentionally) after exit - they may already be being used by another Virtuoso (or other Cadence tool) that was started after the first. If you then killed them off, it would probably break the other Virtuoso sessions that are relying on those daemons (especially cdsNameServer, cdsXvnc; clsbd is more tolerant because it doesn't retain any state information). Regards, Andrew.
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Forum Post: RE: phase noise/vin vs. frequency
Dear skylink, A conventional pnoise analysis with the digital code held as a DC bus value will provide the output phase noise characteristic of a driven circuit. This is a methodology we have used. I do not know if you are using ideal quadrature clocks to drive the phase interpolator or if the clocks originate from other circuits that may contribute phase noise. If the latter is the case, you will need to do a second pnoise simulation of the input clocks to assess their phase noise. My guess is you will need to repeat the output phase noise simulation at a few selected phase steps to validate your assumption about which phase code provides the greatest phase noise degradation. Does this make sense?
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Forum Post: RE: Post Run Simulation Analysis - Plotting wavefroms from different tests
Thank you Andrew! best, EJ
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Forum Post: Virtuoso XL Calculator Multiple Expressions
Hello all, I have a combinatorial circuit with 8-bits of input and output buses and I am trying to find the delay between two buses. My main goal is to find the critical path of my custom designed digital circuit. If I use calculator for finding the delay of separate bits (from 0 to 0 in this case), I use this expression and it works: delayMeasure(leafValue(VT("/in ") "bit" "/in " ) leafValue(VT("/out ") "bit" "/out " ) ) However, I could not find a way to calculate multiple expressions at once as I need to do that for 64 different combinations. If I write two expressions following each other as below, it calculates only the first expression. Am I doing a syntax error or is it not possible to calculate multiple expressions in the calculator? delayMeasure(leafValue(VT("/in ") "bit" "/in " ) leafValue(VT("/out ") "bit" "/out " ) ) delayMeasure(leafValue(VT("/in ") "bit" "/in " ) leafValue(VT("/out ") "bit" "/out " ) ) Thank you for all replies in advance. Hikmet
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Forum Post: mbs2brd or mbs2lib not translate psm, only bsm
Hi, I'm using 17.2's mbs2brd / msb2lib, but I only get bsm from package, I suppose to get psm file. Looks like the translator ignore $$pin instruction ... Does anyone have any experience with this ? Can anyone share geoms_ascii of a component that has been successfully translated to allegro please ? Regards, P.
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Forum Post: RE: how to write a SKILL code for PCELL powergrid
Hi, can anyone please help me with achieving the same pwrgrid pcell using the graphical method of creating a pcell. I want to be able to turn ON and turn OFF specific metal layers and vias. I was able to create the parameter boxes that can be checked/unchecked( in the instance property form). From the Pcell plugin, I dropped down to parameterized layers--> Define. And then I set them to be boolean using Parameters-> Edit. But checking or unchecking the boxes has no effect on the visibility. I know I need to define something more, but don't know what and how to. Can you please help me? I appreciate any help on this.
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