Hi Andrew, I had the hope that something like "putprop( hiGetCurrentWindow() ddsGetLib() 'prop_name)" could work. I will contact to customer support to duplicate the CCR you provided. Thanks and regards, Ivick.
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Forum Post: RE: Hierarchy Editor: Is it possible to add buttons to toolbar?
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Forum Post: RE: Modify dynamic shape parameters using SKILL
I know this is an old thread, but can changing the shape parameters be done on a single shape? axlGetParam("shapeDynamic") works great at the global level, but I need to check and set these parameters for individual shapes. Specifically I am trying to get and/or set the minAperture parameter for all shapes on a specific layer. axlGetParam works on all shapes and it does NOT change a shape that has an override value, which is what I am trying to change. Thank you.
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Forum Post: Computing logarithm in simulator
I am attempting to convert a voltage to dB in the simulation itself. First thought was to create a verilogA block like this: `include "constants.vams" `include "disciplines.vams" module dB20(vi, vo); input vi; output vo; electrical vi; electrical vo; analog begin V(vo) <+ 20*log(abs(V(vi))); end endmodule This seems to work OK for a transient simulations, but in AC sim the output is totally wrong (should be 0, but is 173700 instead). Am I doing something wrong here? If this won't work, is there another way of doing this, like a clever arrangement of analogLib components? Thanks, Steven
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Forum Post: RE: probe tcl command with time_window option
Thanks Andrew. Your suggestion works.
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Forum Post: RE: cds_ff_mpt PDK?
Hi, rsashwinkumar and Andrew I would like to ask if you confront with the problem that there are no "qrc_options.yaml" file while extracting RC via BAG. As I use GUI to extract, there are no problems. Therefore, I went to see bag_config.yaml to check what is going on. I found that there aren't existing "qrc_options.yaml" I use the same pdk(cds_ff_mpt) as you. If you have any instructions, please let me know. here is my email address: rayyeh942@gmail.com Appreciate Sincerely Daniel
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Forum Post: RE: Negative Tolerance in Relative Propagation Delay
thank you , helped a lot
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Forum Post: RE: cds_ff_mpt PDK?
I know nothing about this "BAG" (I had to do a Google search to figure out that this is the "Berkeley Analog Generator"). The missing file is not a file that is needed by our tools, so I assume it must be something to do with this BAG system. You should contact the maintainer of the repository (or use the Issues page on the GitHub project). Andrew.
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Forum Post: RE: The LSSP spectre simulation (Cadence 5) fails with the following error
Thanks for your efforts in answering m When I make a PSS analysis at Cadence SpectreRF, it gives me some warnings related to the breakdown voltage. " Warning from spectre at time = 10.0849 fs during periodic steady state analysis `sweeppss-014_pss ', during Sweep analysis` sweeppss'. M0: Vgd has exceeded the oxide breakdown voltage of `vbox '= 4.08 V. M1: Vgd has exceeded the oxide breakdown voltage of` vbox' = 6.8 V. " However when I test the transient response of the voltage signal between the two related nodes (drain and gate), I found that the voltage does not exceed this value (4.08), as shown in the following figures. Thus, I do not know about the meaning of this error and if the transistor is fabricated it will go to its breakdown region
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Forum Post: RE: cds_ff_mpt PDK?
Dear Andrew, Thanks for your rapidly reply. As for this file, I have already consulted with the maintainer of BAG, and he left a message as showed in the following picture. He said since Cadence doesn't provide the extraction flow of the cds_ff_mpt; therefore, it is hard to set up "qrc_options.yaml", which is the artifact file written in python to let the BAG system run RC extraction automatically. Could I ask about which PDK has provided the supported extraction flow? Or which file is the "extraction flow" of the cds_ff_mpt downloaded from http://pdk.cadence.com . Thanks a lot Sincerely Daniel
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Forum Post: How to convert pnoise to time domain process
The circuit is oscillator, so I am dealing with voltage noise not jitter. I want to get the time domain representation of the noise but the transient noise analysis takes ways too long to simulate. Meanwhile, I get pnoise result very fast even though fmin is very low. I want to ask how to convert pnoise to time domain process without running actual transient noise analysis. Whether doing ifft on the pnoise spectrum gives the time domain process I am looking for.
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Forum Post: Skill program to replace terminal name in layout pin
I'm writing the Skill replace terminal name from VSSPST to VSSH in layout pin. Now I can select the pin but cannot replace. My Virtuoso version is 5.10.41. Any help will be much appreciated.
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Forum Post: RE: cds_ff_mpt PDK?
Hi Daniel, I suspect the maintainer of BAG is talking about an old version of cds_ff_mpt. The 0.3 version didn't have Quantus QRC rules, but the 0.5 version (which is the currently available version on http://pdk.cadence.com ) does have Quantus QRC rules set up: UNIX> /bin/ls -R cds_ff_mpt_v_0.5/qrc cds_ff_mpt_v_0.5/qrc: best corner.defs typical worst cds_ff_mpt_v_0.5/qrc/best: RCXdspfINIT _p2lvsfile cds_ff_mpt_best.ict extview.trp lvsfile RCXspiceINIT callProc.il compilation_cmd layer_setup qrcTechFile cds_ff_mpt_v_0.5/qrc/typical: RCXdspfINIT _p2lvsfile cds_ff_mpt_typical.ict extview.trp lvsfile RCXspiceINIT callProc.il compilation_cmd layer_setup qrcTechFile cds_ff_mpt_v_0.5/qrc/worst: RCXdspfINIT _p2lvsfile cds_ff_mpt_worst.ict extview.trp lvsfile RCXspiceINIT callProc.il compilation_cmd layer_setup qrcTechFile Regards, Andrew.
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Forum Post: RE: Computing logarithm in simulator
Hi Steven, I've been looking into this. First of all, you should remember that the AC analysis is a linear simulation, and it linearises the circuit equations around the DC operating point. Given that log is not a linear function of the inputs, it clearly will not produce the output in dB in the frequency domain - if it was linear, then doubling the input should double the output, which won't be the case if logs are taken. The question now is what it actually does. This is a little odd, and I've not been able to fully explain why the behaviour is as it is. If you'd used ln(abs(V(vi))) (i.e. natural logs and without the multiply by 20) then the output is actually defined as being vi AC /vi DC . My guess is that it has to linearise an impossible to linearise function somehow, and this is how it does it (what I don't know is why this specific representation is used). So the DC value (from the operating point) will influence the result. Now, if you then use log(abs(V(vi))) instead, log(x) is defined as ln(x)/ln(10) and so the output ends up being ( vi AC / vi DC )/ln(10) - and hence if you have this multiplied by 20, you're getting 20* vi AC /(ln(10)* vi DC ). So I'm sure that's what you're seeing - it will be related to the AC and DC values at the node you've connected to this db20 block. Either way, it's not going to do what you want - this is not something you can write a VerilogA model to do in the frequency domain. Regards, Andrew.
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Forum Post: RE: Assura and Quantus options
Thanks Andre that helps. Is there any difference between selecting only DSPF and ' Transistor Dspf" ?
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Forum Post: Cadence License Server Host Id
Hi All, can anyone please let me know how can i check Cadence License Server Host Id ? thanks
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Forum Post: RE: Assura and Quantus options
Yes, which is why there's a choice! DSPF is intended to stop at cell level (e.g. standard cells) and you have to tell it the list of cells, and other information (a few more fields appear). Transistor Dspf goes all the way down to transistor level.
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Forum Post: RE: How to convert pnoise to time domain process
Not entirely sure why it being an oscillator means you're interested in voltage noise rather than jitter - normally with oscillators (since they are amplitude limited) it's normally the voltage noise at the transitions that matter, i.e. the PM rather than the AM noise, which results in phase noise or jitter. Either way, not sure that's important for your question. Why do you want to convert this back into the time domain? The noise output from pnoise analysis gives you the power spectral density of the noise, and so in transient noise you'd only see a similar shape after averaging over multiple cycles (because it's random) - seeing a single period in the time domain is not going to be terribly useful (I'd have thought). There is the ability with the "Sampled Phase" mode of "sampled" pnoise (formerly known as tdnoise or time domain noise as the Noise Type in older versions) to sample the noise at various strobe points throughout the period. This adds a sampler at the output of the circuit and allows you to see how the noise varies throughout the period (so you can see the noise PSD at instants in time throughout the period, for example). Not sure if that's what you want though. So put simply, I'm not sure what your real objective is here, so I don't know how to answer! Regards, Andrew.
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Forum Post: RE: Skill program to replace terminal name in layout pin
If you use the graphical search and replace form in the layout editor to search for pins, you'll see that there are no choices to replace anything having found the pins. So this is not supported in IC5141. I see that in newer versions, it is supported (in IC618 for example). The perils of using software released 16 years ago... Andrew.
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Forum Post: RE: The LSSP spectre simulation (Cadence 5) fails with the following error
Sometimes these messages occur as PSS is trying to converge. The Shooting Newton method is trying to solve for the final settled steady state of the circuit, and sometimes as it is iterating towards a solution, it will move the operating region outside the correct place and then you might see these breakdown type messages. Usually you wouldn't expect to see that in the final iteration though when it reaches convergence - you should check the time domain waveforms from the final PSS solution to see if they appear to be in the correct region (it would be odd for it to converge in an invalid region though unless the models are non-physical). So usually this is nothing to worry about, just an indication that the circuit is a little problematic to converge. Regards, Andrew.
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Forum Post: RE: Assura and Quantus options
thank you very much for the information.
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