You can only import artwork files if generated from Allegro or OrCAD PCB editor. File - import - artwork option will help.
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Forum Post: RE: to import Gerber file with .dat, , .gbl and .art extension into APDL
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Forum Post: RE: Allegro design entry DHL, pin swaps , export without exporting constraints, back annotate.
You can find the documentation of all these within the tool. Help- Documentation, and search design entry HDL wherein you can user guides helping you solve the query
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Forum Post: RE: Skill program to replace terminal name in layout pin
Hi Andrew. Thanks for your prompt reply
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Forum Post: RE: How to convert pnoise to time domain process
Sorry, I made a typo. I meant "not oscillator", an amplifier for example. The reason why I want to convert it back to time domain is because the specification is in time domain. I am not so confident the integrated noise from noise summary is 1:1 to what I want to "the way I want to measure" in time domain. At least, I want to "measure" the deviation in time domain to at least get confidence level that it matches with integrated pnoise roughly.
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Forum Post: RE: How to convert pnoise to time domain process
Well, I don't think you can really convert back into the time domain anyway, so this is probably a moot point. Often time domain metrics would be to measure the RMS noise power, which should be similar to the integrated noise power. Perhaps you can compare with transient noise to convince yourself that the results are reasonable (generally speaking though there's more scope for inaccuracy with transient noise if you don't set it up right - e.g. not high enough fmax, or not a long enough simulation, or not high enough accuracy to resolve the small noise signals). Andrew.
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Forum Post: RE: Cadence License Server Host Id
Normally you'd look at your $CDS_LIC_FILE env var to see what host the license server is running on - it's often in the form 5280@hostname - or failing that, $LM_LICENSE_FILE (generally we advise against using the generic FlexLM env var, as it's better to use the Cadence-specific env var). Then on that host, check for running "lmgrd" processes and find out which license file they are reading - and at the top of that license file you can see a "DAEMON" line which will give the hostid of the machine (running lmhostid on the same machine should also give the hostid too). Andrew.
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Forum Post: Regarding Monte-Carlo Simulations
Hi, I have implemented a Common Source amplifier with current load. After simulating gain, now I want to go for Monte-Carlo Simulations for knowing statistical parameters. I have few questions? 1. What is the exact criteria for selecting number of runs of MCS? For some circuits MCS runs are selected as 100. Why the number of runs of MCS are selected as 100? 2. Is 100 times of MCS enough for predicting the possible performance of the circuit if it is manufactured later? 3. How to make sure number of runs (100 runs of MCS) are necessary for precise prediction? 4. If I simulate some bigger circuit say OTA etc. Shall I need to increase number of MCS runs? 5. Is there any literature (Book) available to support selection of no. of MCS runs for particular circuit? Looking forward for kind help and suggestions. Regards!
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Forum Post: RE: Regarding Monte-Carlo Simulations
Trying to guess an appropriate number of Monte Carlo points is very hard. How many is enough will depend on your yield target - the higher the yield target, the more points you are likely to need. I don't know why 100 would be chosen (100 is somewhat arbitrary, and it's almost certainly not enough for any reasonable yield target, but it may give you a reasonable idea about the sensitivities of your design). In general you want to use the yield verification choice when using ADE Explorer/Assembler. The Monte Carlo setup form for ADE Explorer/Assembler now asks you what you're trying to do - and it can do three things: Run a fixed number of points. This assumes you have a fixed budget (maybe time) for simulations and so you need to get a rough idea but aren't being very precise about the yield Verify the yield - you can then enter the yield target as either a percentage or in sigma, and it will run enough simulations to be confident that it either meets or fails to meet the target. By default it would use the Virtuoso Variation Option license to allow sample reordering to efficiently run the worst samples first, but you can also choose "basic auto stop" on the advanced options which can be run without an additional license (it will still be able to stop early if the confidence limit has been reached, but most likely will need more simulations than the sample reordering flow). The yield verification also supports high-sigma (e.g. up to 6 sigma) methods which use a different approach. Don't be tempted to say that your yield target is 100% because that needs an infinite number of simulations ;-). All of this requires you to have specifications on your output measurements, by the way. Statistical Corner creation - this is an automated way to get (say) 3 sigma corners for each of your measurements. These can then be used in non MC sims to tune your design. A good place to understand all this is in the Rapid Adoption Kit here: Advanced Statistical Analysis for Variation Aware Design Regards, Andrew.
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Forum Post: Please suggest a good begineer book or video tutorial series on Cadence Allegro APD/SIP in english.
Please suggest a good begineer book or video tutorial series on Cadence Allegro APD/SIP in english.
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Forum Post: RE: Regarding Monte-Carlo Simulations
I am thankful to you for guiding so well.
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Forum Post: RE: How to convert pnoise to time domain process
Dear Excalibur, If I may intrude a bit on your question and your need for a “time domain” representation (and perhaps add to Andrew’s responses). Even a specification such as an rms noise is defined over a limited bandwidth. Hence, you need the frequency domain information to determine if your amplifier meets its requirement. If you recall, Parseval’s theorem expresses the equivalence of the energy in the time and frequency domain results for a signal. Hence, I also agree with Andrew that converting from the frequency domain to the time domain should not be necessary with enough knowledge about the actual circuit requirement for your amplifier. Shawn
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Forum Post: RE: Regarding Monte-Carlo Simulations
Dear Kabes, For your information, my approach to answer your question regarding what is considered a “sufficient” number of Monte Carlo simulations is to initially perform a very large number of Monte Carlo simulations on a small circuit whose statistical behavior mimics the circuit under study. If your circuit under study is small, you could simply use it. Using the raw output data for the parameter of interest, I compute the estimate of the standard deviation as a function of the number of simulations and plot the result. I have attached an example of such a result. From this data, and knowing the statistical requirements for your estimate of the standard deviation, you may better estimate the number of Monte Carlo simulations to perform. Does this address your question? Shawn
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Forum Post: RE: Allegro design entry DHL, pin swaps , export without exporting constraints, back annotate.
There's a "Rapid Adoption Kit" or RAK that should walk you through the entire workflow, with a lab database you can download from the Cadence support website. https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050NrEAI&pageName=ArticleContent
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Forum Post: RE: Regarding Monte-Carlo Simulations
Thanks for your reply. I will work with this strategy.
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Forum Post: pcellEvalFailed when I change my cadence version
Hi Andrew, I am trying to run the post layout simulations for my project. Everytime I run Assura QRC it fails, I tried to change the cadence version from 6.1.7 to 6.1.5 to see if it works or not, but when I open the layout which is DRC and LVS clean, the compnents are disappeared and I cannot event bring them manually in the layout and the following warning/error pops up: WARNING* (DB-270001): Pcell evaluation for PRIMLIB/ne/layout has the following error(s): *WARNING* (DB-270002): ("eval" 0 t nil ("*Error* eval: undefined function" XpcInitMosfet)) *WARNING* (DB-270003): Error kept in "errorDesc" property of the label "pcellEvalFailed" on layer/purpose "marker/error" in the submaster. Do you have any suggestions that what is happening? Regards, Mehdi
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Forum Post: Cadence License Server Host Id
Hi All, can anyone please let me know how can i check Cadence License Server Host Id ? thanks
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Forum Post: Main Transistors from technology file are missing after QRC Extraction
Hi, I have run parasitic extraction on a simple inverter in a new technology that I have. After running the post layout simulation using Assura, the main transistors are missing in the analog extracted view. I have also checked the netlist and there are only the parasitic resistances and capacitance. What do you think might be the issue? Is it from the technology file? Regards, Mehdi
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Forum Post: TensorFlow Lite Micro (TFLM) sample application for the HiFi4 DSP
Please, I am trying to implement a sample TFLM application on an evaluation board which has a Cadence Tensilica HiFi 4 DSP. Please, is anyone aware of a repo where i could find a sample application with details of building a simple model and deploying it on the HiFi DSP using TensorFlow tool chain.
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Forum Post: Mapped to external links for text files opened with view() skill function
Hi, When a simulation log file is opened from ADE-L it is opened in a viewfile window and highlights with links (which red tooltips say at the end "Mapped to external") a couple of lines like warnings, errors, paths, simulator options and even probe signals. However if I open the same file by using the view() function, the text is displayed as plain text without any highlight link, even I tried to open the file by using hiOpenWindow() with ?type as hypertext or html but no link is shown either. Could you please tell me (if exists) a way to open simulator log files with a function like view() or hiOpenWindow() in order to show the the highlight links likewise ADE-L does? btw. I found the following ticket however the log file does not have any hypertext and even so ADE-L opens it with highlighted links (Does maybe ADE-L auto create a hypertext file based on the plain text of the log file behind scene?) https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/28984/create-a-clickable-report-in-skill/1334421#1334421 Thanks and regards, Ivick.
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Forum Post: RE: Main Transistors from technology file are missing after QRC Extraction
Here is the netlist after and before the post layout and also the screen shot of the layout and post layout for your reference: before post layout: // Library name: Testing // Cell name: inverter // View name: schematic // Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl //pspice dspf subckt inverter_schematic VDD VIN VOUT VSS M0 (VOUT VIN VSS VSS) ne w=220.0n l=180.0n as=1.056e-13 ad=1.056e-13 \ ps=1.4e-06 pd=1.4e-06 nrs=1.22727 nrd=1.22727 m=(1)*(1) \ par1=((1)*(1)) M1 (VOUT VIN VDD VDD) pe w=220.0n l=180.0n as=1.056e-13 ad=1.056e-13 \ ps=1.4e-06 pd=1.4e-06 nrs=1.22727 nrd=1.22727 m=(1)*(1) \ par1=((1)*(1)) ends inverter_schematic // End of subcircuit definition. // Library name: Testing // Cell name: inverter_TB // View name: schematic // Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl // pspice dspf I0 (VDD IN OUT 0) inverter_schematic V0 (IN 0) vsource dc=0 type=pulse val0=0 val1=1 period=20n rise=10p \ fall=10p width=10n V1 (VDD 0) vsource dc=1 type=dc simulatorOptions options reltol=100e-6 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 homotopy=all limit=delta scalem=1.0 scale=1.0 \ compatible=spice2 gmin=1e-12 rforce=1 redefinedparams=warning \ maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \ sensfile="../psf/sens.output" checklimitdest=psf tran tran stop=100n errpreset=conservative write="spectre.ic" \ writefinal="spectre.fc" annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile save IN OUT saveOptions options save=allpub Analog Extracted Version: // Library name: Testing // Cell name: inverter // View name: analog_extracted // Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl //pspice dspf subckt inverter VDD VIN VOUT VSS c1 (\1\:VIN VDD) capacitor c=7.38154e-17 m=1 c2 (\1\:VDD \1\:VIN) capacitor c=1.83121e-17 m=1 c3 (VOUT \1\:VIN) capacitor c=3.76045e-17 m=1 c4 (\2\:VSS \1\:VDD) capacitor c=2.28712e-17 m=1 c5 (VOUT VDD) capacitor c=4.18425e-17 m=1 c6 (\2\:VSS \1\:VIN) capacitor c=1.82276e-17 m=1 c7 (\1\:VDD VOUT) capacitor c=3.1724e-17 m=1 c8 (\2\:VSS VOUT) capacitor c=5.31049e-17 m=1 c9 (VOUT VSS) capacitor c=5.63461e-17 m=1 c10 (\1\:VIN VSS) capacitor c=8.61706e-17 m=1 rf1 (\1\:VDD \3\:VDD) resistor r=0.01913 m=1 rf4 (\3\:VDD \1\:VDD) resistor r=0.09757 m=1 rf5 (VDD \1\:VDD) resistor r=0.01576 m=1 rf8 (\2\:VDD \3\:VDD) resistor r=7.5 m=1 rf9 (\2\:VDD \3\:VDD) resistor r=7.5 m=1 rf13 (\2\:VSS VSS) resistor r=0.05234 m=1 rf14 (\2\:VSS \7\:VSS) resistor r=0.0735 m=1 rf16 (\7\:VSS \2\:VSS) resistor r=0.002888 m=1 rf17 (\1\:VSS \2\:VSS) resistor r=7.5 m=1 rf18 (\1\:VSS \2\:VSS) resistor r=7.5 m=1 rg1 (\1\:VIN VIN) resistor r=0.6904 m=1 rg2 (VIN \1\:VIN) resistor r=0.1014 m=1 ends inverter // End of subcircuit definition. // Library name: Testing // Cell name: inverter_TB // View name: schematic // Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl // pspice dspf I0 (VDD IN OUT 0) inverter V0 (IN 0) vsource dc=0 type=pulse val0=0 val1=1 period=20n rise=10p \ fall=10p width=10n V1 (VDD 0) vsource dc=1 type=dc simulatorOptions options reltol=100e-6 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 homotopy=all limit=delta scalem=1.0 scale=1.0 \ compatible=spice2 gmin=1e-12 rforce=1 redefinedparams=warning \ maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \ sensfile="../psf/sens.output" checklimitdest=psf tran tran stop=100n errpreset=conservative write="spectre.ic" \ writefinal="spectre.fc" annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile save IN OUT saveOptions options save=allpub
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