Dear Andrew, I got you. I will provide this information to the maintainer and discuss it with him. Thanks a lot. You save me lots of time!! Sincerely Daniel
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Forum Post: RE: cds_ff_mpt PDK?
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Forum Post: Step model "skinning" export in 17.4?
I found a mention in the 3D notes but wondering if the feature has been released for 17.4 sp6... Anyone find it?
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Forum Post: Can Cadence Incisive Enterprise Verifier be used for functional verification?
I understand that Cadence Incisive Enterprise Verifier is for Assertion Based Verification, it has within it In cisive Enterprise Simulator which lets the tool generate testbench stimulus from assertions and thus gives dual benefit of formal and functional verification. My doubt is if I can use the tool exclusively for functional verification? That is I have a set of test benches that are already written, and I need to just simulate it just like we do in modelsim. Is it possible to do in Incisive Enterprise Verifier? If possible, please give insights on where I can refer on how to do that. I can't find details on this topic in the manual or user guide.
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Forum Post: RE: Schematic lost on Allegro Design Entry CIS [ERROR(ORCAP-1153)]
Al Gore said he invented it. Direct quote.
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Forum Post: Plotting waveforms with skill
Hi, I have a bunch of PSF directories in file "waveforms.txt". I have a bunch of expressions in file "expressions.txt". What I am trying to do is plotting each expression from all the results(i.e, PSF directories mentioned in waveforms.txt) in new window of Viva. This is the problem statement. Now, Sample Waveform : /psf/ Sample Expression: v("/voltage_input" ?result "tran") //voltage_input is net name // Here is the code I have written // Code starts // cr=pcreCompile("\n") vvDisplayCalculator(list()) expressions = infile( "expressions.txt" ) when( expressions while( gets( nextLine expressions ) expression_to_plot=pcreReplace(cr nextLine "" 0) println( expression_to_plot) waveforms = infile( "netlists.txt") when( waveforms while( gets( next_waveform waveforms ) waveform_to_plot_from=pcreReplace(cr next_waveform "" 0) println( waveform_to_plot_from) rdbLoadResults("unbound" waveform_to_plot_from) println("waveform is loaded") _vivaSetDataContext(waveform_to_plot_from) println("Context is set") awvPlotSimpleExpression(expression_to_plot) println("Expression is plotted") ) close( waveforms) ) awvCreatePlotWindow() ) close( expressions ) ) // Code Ends // it throws error saying this *Error* ilGetString: arg must be symbol or string - nil *Error* error: SKILL ERROR - nil *Error* load: error while loading file - "proper.il" at line 34 Could you help me here ???
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Forum Post: Reliability analysis - custom models
Dear guys, I am trying to perform reliability analysis in Cadence Virtuoso, however the foundry do not provide AgeMOS models for process node, I use. So my question is: Is there please a workaround to reach at least approximate results of NBTI, HCI, ageing effects on circuit? For example, I suppose I could define analytical equations of mentioned phenomenons. Results will be far from fitting real data, but I need to see just a trend. If there is similar solution, somebody can explain me, my tremendous thank would belong to him :) I work in Cadence 6.1.7. Kind regards, Michal Sovcik
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Forum Post: create or delete subcell from CDF callback
A pcell can instantiate subcells at creation. Is there a way to add or remove them via a CDF parameter through the callback? For example, say I have a resistor that gets added to, or removed from, a schematic based on a CDF parameter. Thanks, Steven
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Forum Post: RE: How to convert pnoise to time domain process
Well, I don't think you can really convert back into the time domain anyway, so this is probably a moot point. Often time domain metrics would be to measure the RMS noise power, which should be similar to the integrated noise power. Perhaps you can compare with transient noise to convince yourself that the results are reasonable (generally speaking though there's more scope for inaccuracy with transient noise if you don't set it up right - e.g. not high enough fmax, or not a long enough simulation, or not high enough accuracy to resolve the small noise signals). Andrew.
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Forum Post: RE: create or delete subcell from CDF callback
I would suggest to create the subcell conditionally as part of the PCell creation code. Something like: (when (dbCreateInstance ...)) And then provide a CDF param for that PCell parameter.
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Forum Post: Any angle routing in Allegro PCB 17.4
Does Allegro support any angle routing? I used offset routing where I could set an angle between 4-18degree. Say suppose I want to use 24degree or any other value how can I route it. I am using Allegro PCB Designer 17.4 006
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Forum Post: RE: How to add PSpice model to CIS component?
Thanks for sharing the nice post. The USPS LiteBlue website is an official portal for the employees of the United States Postal Services (USPS) for easy information flow and faster communication. liteblue.usps.gov
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Forum Post: RE: How to convert pnoise to time domain process
Hi ShawnLogan, I do not understand why " Even a specification such as an rms noise is defined over a limited bandwidth ". How I see it is just measuring the noise during a defined time window, e.g. 1us. The frequency content is of no relevance, e.g. is it 90% 1/f and 10% white noise or is it 10% 1/f noise and 90% thermal noise. I do know Parseval’s theorem. The trick is, the theorem is about when time is infinite and when frequency is infinite. It does not apply to a process that is limited in time. I read quite some papers on this topic. The impression I get is that the power of a time domain process start from t=0, e.g. noise, at a time T is equal to integrating the process's spectrum from f=1/T to f=+inf, scaled by some factor involving pi. Of course, if somebody took the task of translating time domain spec to the amplifier noise spec, then I dont need to deal with time domain here.
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Forum Post: data.dm in cell, which view type is depend on it?
Hi, I am writing a design hierarchy analyser for data management, for example for check out, label or some check of design files. I will get all files from a design hierarchy. Is there any exists function for that? In my code I am not sure, wenn should I add the data.dm of cell level to the list. Is there any list where is defined, which cell type is depend on the data.dm? Or I have add the data.dm for all layout type to the list? Importent is the type schematic, symbol and layout. best regards Ke Yang
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Forum Post: Too many Point Sweeps (>1 M) for ADE XL to handle
Hi, I'm new to ADE XL, and not sure whether I am asking a dumb question.. I'm trying to use ADE XL to sweep a parametric set of 10 variables, each having 5 values to sweep over. So effectively there should be only 5 runs of simulation. However, the "Run Summary" shows there will be 9.765625e+6 (i.e. 5^10) Points Sweeps which is over the hard limit of 1e+6. So cannot launch the job (Single Run, Sweeps and Corners), as below: I am pretty sure I have already grouped the 10 variables into one parametric set. When I reduces the number of values per variable from 5 to 3 (thus the total point sweeps is now 3^10=59049 <1e+06 ), the job can be launched, and as expected only 3 runs of simulation. I cannot believe ADE XL cannot handle the above simple user cases. So what mistake do I make? Thanks for help in advance! Brayden
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Forum Post: RE: Too many Point Sweeps (>1 M) for ADE XL to handle
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Forum Post: RE: Too many Point Sweeps (>1 M) for ADE XL to handle
Which IC subversion (Help->About tells you this) are you using? It doesn't happen with the current version (IC618 ISR11) so I want to check with whatever version you're using (in case it has something to do with the submit point being enabled, which isn't present in current versions). Andrew.
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Forum Post: RE: Any angle routing in Allegro PCB 17.4
Yes, start routing then click on the P icon at the bottom of the screen, you can then change the setting to distance + angle and type say 10 24 (for a 10mm line at 24 degrees).
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Forum Post: RE: Can Cadence Incisive Enterprise Verifier be used for functional verification?
IEV is a legacy tool for formal property checking. You're right that it does include the IES simulator component as well to allow you to simulate regular behavioural testbenches as well, but IEV's primary role is for property checking. If you're struggling to find information on this, login to support.cadence.com and look for the Incisive Enterprise Simulator 15.20 User Guide . You should find it under the Resources -> Product Manuals drop-down menu at the top of the screen. If you've already got a simulation environment for Modelsim, then it should be fairly simple to take the same set of source files and pass them to the "run" command for Incisive. Run is a front-end for compiling and simulating the code. Some options will be common, but if you have any Modelsim switches that are proprietary to Modelsim, you'll need to look at the iron user guide to understand how to convert those to something compatible with Incisive. Your local Cadence AE can help with that, if you need help. Note that Incisive is a legacy tool, it was replaced by Xcelium in 2016, and Cadence can only provide very limited support for Incisive now, so if you have the option, please try to use Xcelium.
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Forum Post: RE: Step model "skinning" export in 17.4?
No sure about export but you can enable this for the 3d canvas view: " You can now use skinning along with some of the already existing options in getting large designs into 3D Canvas. Skinning is the loading of only the external components and layers in 3D Canvas. Set 3D_canvas_skinning under Setup – User Preferences – Display – 3D to turn on skinning."
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Forum Post: RE: Mapped to external links for text files opened with view() skill function
This is a bit beyond just an HTML file because some of the hyperlinks cross-probe to the schematic. You can create an HTML file and use the HTML view file window (see hiCreateWIndow for documentation). In this case it's a special widget specifically for Spectre, and it's launched using a (private) Spectre function tied to the ADE (SEV) session rather than being passed the log file (it needs to know the corresponding schematics to get the cross-probing done, for example). Andrew.
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