Dear All, I want to use a transformer in both cadence spectre and virtuoso, My used Technology does not have its own Transformer. How I can Activate the mutual coupling between two Technologu's spiral Inductors in schematic and layout as well. is this possible ? or I have to build my own transformer using another EM-simulator and then importing its S-parameter block to the cadence environment. Regards
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Forum Post: Transformer and Mutual Coupling
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Forum Post: PCB Editor 17.4, no XNETs after model assignment
Hello, I have created a schematic in Capture 17.4 and successfully created a netlist then imported into PCB Editor 17.4 and placed all components. I want to create constraints using Constraint Manager but am having a problem with XNETs. Many of the constraints will be relative prop delay for signals which start at a connector, pass through a resistor then end at an IC. The rats all looked as expected so I think the schematic is correct. When I opened CM it showed a lot of XNETs but each XNET only had one net (the one from resistor to IC). I realized that the resistors did not have models assigned, so I created and assigned a model to all of them (used standard 2-pin model with 0.001 ohm value). After doing that and opening CM again the XNETs had changed to NETs and there were no XNETs. I tried importing again after assigning models but nothing changed. [Q] Why are nets shown as XNETs after the initial import when no models are assigned? [Q] Why do I not see XNETs after assigning resistor models in PCB Editor? Thanks for any suggestions.
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Forum Post: 3D drill size ?
When I measure the finished hole diameter in the 3D the software starts with the finished hole size and then adds the layer thickness to the hole. So for example a 40 mil finished hole with 1 OZ Copper plus plating ends up a 34.8 mil hole. The value for the drill is the finished hole size , not the starting hole size before plating. Usually the plating process only adds 1.4 . Is this just a bug or is there a way to fix this ?
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Forum Post: Mutual Coupling
Dear All, I want to build a transformer. I use "mind" tool from analoglib Library to assign a mutual coupling between two ideal spiral inductors in schematic. However, it fails with other technology's Inductors. I can not use this tool in both schematic and Layout design, is there any solution to build my own transformer in schmeatic and layout as well. or should I build and simulate it using another EM-simulator and import it in my schematic as (Two-Port) s-parameter file? Thanks in advance.
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Forum Post: [AWR Microwave Office] PAE vs Back-off graph
Hello everyone, I've some question related to the AWR Microwave Office. I want to calculate relation between PAE and Back-off of a Doherty amplifier. I saw on the internet some graphs on which such thing has been presented - I'm sending bellow some example: It is possible to draught such a graph in AWR ? Best Regards, E.
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Forum Post: How to suppress/cancel port mismatch popup window when running vmsUpdateCellViews/ahdlUpdateViewInfo
Hi, I am doing batch compile of veriloga views, and getting a "Port mismatch" popup window. I am using currently ahdlUpdateViewInfo function for VerilogA but I tried also vmsUpdateCellViews and getting the same popup How can I prevent it from appearing or auto-cancel it? I found this topic: https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/36380/suppressing-hdl-parser-warning-and-port-mismatch-warnings/1348507 But setting envSetVal("schematic" "disablePortOrderPopup" 'boolean t) envSetVal("schematic" "vicCheckPinOrder" 'boolean nil) vmsCrossViewCheck=nil Does not prevent popup window. I tried also: schHdlCrossViewCheck = nil vmsUpdateSymbolAfterEdit=nil AHDLUpdateViewInfo=nil vmsRunningInUI=nil With no success. Thanks!
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Forum Post: RE: How to suppress/cancel port mismatch popup window when running vmsUpdateCellViews/ahdlUpdateViewInfo
Hi Alex, I think it depends which popup it is. One of them can't be suppressed, if I remember rightly - so it's probably best to understand precisely what you're doing and then we can see how to fix/workaround it. Perhaps you can contact customer support? Andrew.
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Forum Post: Adding menu in Constraint Manager
Can anyone tell me how to add a menu in the constraint manager ? Adding a menu in Layout or Symbol is simple enough but I have not found any reference to menus in the CM. Jim O'Mahony
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Forum Post: RE: How to suppress/cancel port mismatch popup window when running vmsUpdateCellViews/ahdlUpdateViewInfo
Hi Andrew, It should be easy to reproduce. If you have a cell with a schematic view and veriloga view with different ports, and you calling ahdlUpdateViewInfo(destLib ?cell destCell ?view destView) There will be this popup: I can, of cause, contact support. But from my experience they not very helpful in cases like this.
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Forum Post: possible to add other reports to "Status" report?
One report that I occasionally forget to run is the "single-pin net report". The times I forget it is when I should have. I'd like to add that to the reports automatically run during "status". Is it possible to modify this or is there some other way folks do it so they don't forget?
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Forum Post: RE: possible to add other reports to "Status" report?
If you want to add a menu you could start by reading the following blog https://community.cadence.com/cadence_blogs_8/b/pcb/posts/make-menus-your-own-customizing-menus-and-toolbars-with-things-you-use-daily I use the following code (saved in a .il file) to output some reports axlCmdRegister( "final checks" 'FinalChecks ?cmdType "general") defun( FinalChecks () let( ( final_verif ) final_verif = axlDMOpenFile("TEMP", "final_verif.scr", "w") fprintf( final_verif "version 17.2\n") fprintf( final_verif "\n") fprintf( final_verif "setwindow pcb\n") fprintf( final_verif "generaledit\n") fprintf( final_verif "status\n") fprintf( final_verif "generaledit\n") fprintf( final_verif "setwindow form.status\n") fprintf( final_verif "FORM status drc_update\n") fprintf( final_verif "generaledit\n") fprintf( final_verif "reports \"Dangling Lines, Via and Antenna Report\"\n") fprintf( final_verif "reports \"Net Single Pin and No Pin\"\n") fprintf( final_verif "reports \"Shape No Net\"\n") fprintf( final_verif "reports \"Shape Islands\"\n") fprintf( final_verif "reports \"Unconnected Pins Report\"\n") fprintf( final_verif "reports \"Design Rules Check (DRC) Report\"\n") fprintf( final_verif "reports \"Design Rules Net Shorts Check (DRC) Report\"\n") fprintf( final_verif "reports \"Waived Design Rules Shorts Check (DRC) Report\"\n") fprintf( final_verif "setwindow pcb\n") axlDMClose(final_verif) axlShell("replay ./final_verif.scr") if( isFile("./final_verif.scr") then deleteFile("./final_verif.scr")) );let ); defun Search the forum for how to add menus and automatically load skill files. Jim O'Mahony
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Forum Post: How to create the biggest rectangle inside a Polygon
Hello everyone! I need a function where the input is a list of points that represent a polygon and the output is a list of 4 points that represent the biggest rectangle that fits inside the original polygon. Does anybody know an existing function for that? Thanks
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Forum Post: Pin placement is giving me trouble
Good evening, i am trying to automatically place pins in the layout XL enviroment using the Place->Analog->adjust cell pins. But as you can see in the picture below i am not obtaining great results: the automatic tool is placing the pin (the small blue dot at the center of the picture) outside the metal drawing of the net. To me it seems like the tool is placing the pin at the center of an hipotetic big square. I've tried to use the tool place-> Pin Placement and setting the edge as level-1 pin, but it's not working. What i would like to do is to automatically place the pins on its metal drawing, possibily matching the geometry. I've tried to consult the manuals and the help, but i am able to solve the problem. Do you have any tips? i am using virtuoso 6.1.7 Many thanks Best Regards, Andrea
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Forum Post: RE: Shift3 bindkey not working
Hi there, Many years after that post I still have this issue. Originally - back in 2012 - I thought that was the issue with the German keyboard layout I was using as on SHIFT+3 was asigned a different symbol and thus my key programming was not overwriting the embeded bindkey. I was deleting the default value and then I had a functional SHIFT+3 bindkey. Since a few months ago, this is not working. There is no other bindkey assigned - yet SHIFT+3 does not work. Can you please guide me through that? Many thanks, BR, D.
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Forum Post: Conformal Litmus vs JasperGold CDC
Hi, What is the CDC tool from Cadence ? It looks like there are at least 2 choices when googling the internet. 1. What are the difference between Conformal Litmus vs JasperGold CDC ? 2. Does Incisive HAL have any CDC checking ? Appreciate any feedback. Thanks, Chris
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Forum Post: RE: How to create the biggest rectangle inside a Polygon
There's nothing built-in to do this. I was chatting about this with my team, and I'm not sure a general algorithm to find the largest rectangle within an arbitrary polygon is that easy. There may be multiple solutions for a start, and it could be that the points of the rectangle don't coincide with any points in the polygon. So the simple answer is I'm not aware of anything to do this, or even an algorithm to compute this. I did a quick google search too, and there are a number of papers and discussions on this - like this for example. Of course, if there are some specific constraints on this rectangle or on the polygon - then a simpler method may be possible. Either way, there's no built-in function for this AFAIK. Andrew.
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Forum Post: RE: Allegro Free Viewer
Thank you for this great contribution, I find it very interesting and well thought out and put together. I hope to read your work in the future. Cyberpunk 2077 Jacket
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Forum Post: RE: Conformal Litmus vs JasperGold CDC
Hi Chris, On the which CDC question, the answer closely ties to your role. If you are more on the implementation side and familiar with that toolset, Conformal Litmus would likely be your tool. However, if you are more on the RTL DV verification side, Jasper is likely your tool. Given your question about HAL, I’m assuming the latter. As far as HAL, there are very basic CDC checks which can be useful but not likely sufficient for signoff. More details can be found in the “HAL User Guide” on COS (Cadence Online Support – https://support.cadence.com ) But please feel free to reach out to me directly ( ckomar@cadence.com ) to discuss further. Thanks, Chris
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Forum Post: RE: Getting lines on Assembly Top for a symbol
Awesome thank you very much David! I just tried out the code, and it works well. Its almost what I want- This code returns the bounding box for all lines on Assembly Top, per placed symbol. If possible, I'd like to get the bounding box for each individual line, so that I can determine which size RefDes will fit. For instance, on An SOIC componenent, there's lines forming the body of the part, and lines forming the pins. The bounding box for all lines would include area covered by the pins, and I'd like the Refdes to fit inside the body of the part. Not a good example but you get the idea. For some other parts, say an SMB jack, theres lines forming the body, but then a circle at the center for center pins, where a RefDes would interfere. Is it possible to get the coordinate info for each line? I guess another way of looking at it would be- starting at the symbol center, what are the coordinates for the largest bounding box that can fit before intersecting a line on Assembly Top? Thank you so much brother! Cheers!
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Forum Post: RE: Mutual Coupling
Dear Omar, I am afraid I do not understand your comment: [quote userid="473568" url="~/cadence_technology_forums/f/custom-ic-design/46781/mutual-coupling"]However, it fails with other technology's Inductors.[/quote] Are you suggesting you are unable to schematically add mutual coupling between two distinct inductors (i.e., not instances of an "mind" from the analogLib) placed on a schematic? Certainly, you cannot layout an "mind" component from the analogLib library as there is not a unique relationship between its performance and its physical geometry. Typically, the layout of an inductive based element is created with its model based on its layout in an EM simulator that can simulate its characteristics. From that an S-parameter or SPICE model can be created and used in a Cadence schematic simulation. You might also consider creating a verilogA model of an inductive based component. There is a paper detailing such a methodology with Ken Kundert as one of its authors at URL: designers-guide.org/.../mag.pdf Shawn
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