Hi Chris, Thanks a lot for your feedback. As your guess, my background is logic design. However, I am trying to evaluate a proper flow for my company and would like to know more about the details. Further questions : 1. Are both tools using the same core/engine ? Is there any comparison table about these 2 tools that you can provide the link ? It would be good to know the pros and cons of each tool ? 2. I also found this " Conformal Extended Checks " . How is this different from above 2 tools ? Thanks, Chris
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Forum Post: RE: Conformal Litmus vs JasperGold CDC
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Forum Post: RE: possible to add other reports to "Status" report?
That sir is beautifully written SKILL code! Finally something not looking like an obfuscation contest :)
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Forum Post: Netlist property syntax warnings after back annotation, then netlist re-import
My toolset is OrCad PCB Editor 17.4-S009. I recently performed a back annotation from PCB Editor to Capture, then re-generated a netlist in Capture to import into PCB Editor (to be sure they are synced). When I imported the netlist into PCB Editor, I have the following new warnings: ------ Oversights/Warnings/Errors ------ #1 WARNING(SPMHNI-316): Property warning detected. WARNING(SPMHNI-217): Problems with net 'D1_MA11'. Error with net property 'RELATIVE_PROPAGATION_DELAY' and value 'MG_DDR4_ADDR_5:G:U16.N2:U21.N2:::MG_DDR4_ADDR_4:G:U9.N2:U16.N2:::::': 'expected syntax is : : : : : '. #2 WARNING(SPMHNI-316): Property warning detected. WARNING(SPMHNI-217): Problems with net 'D1_MA2'. Error with net property 'RELATIVE_PROPAGATION_DELAY' and value 'MG_DDR4_ADDR_3:G:U6.M3:U9.M3::::': 'expected syntax is : : : : : '. #3 WARNING(SPMHNI-316): Property warning detected. WARNING(SPMHNI-217): Problems with net 'D1_MBA1'. Error with net property 'RELATIVE_PROPAGATION_DELAY' and value 'MG_DDR4_ADDR_6:G:U21.K8:R131.1:::::::': 'expected syntax is : : : : : '. #4 WARNING(SPMHNI-316): Property warning detected. WARNING(SPMHNI-217): Problems with net 'D1_MCK1_B'. Error with net property 'RELATIVE_PROPAGATION_DELAY' and value 'MG_DDR4_ADDR_6:G:U38.F8:R136.1:0.00 MIL:5.00 MIL::::MG_DDR4_ADDR_2:G:U31.F8:U33.F8:::MG_DDR4_ADDR_1:G:U5.AC29:U31.F8::': 'expected syntax is : : : : :<tole I performed a DBDoctor update through the external application with no change. Any idea on how to resolve? Prior to this, I had no DRC errors at all.
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Forum Post: RE: Mutual Coupling
"Are you suggesting you are unable to schematically add mutual coupling between two distinct inductors (i.e., not instances of an "mind" from the analogLib) placed on a schematic?" That is right? Is there any solution for this problem, or as you mentioned that using S-Parameter , imported from EM-simulator, is the best solution for that problem?
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Forum Post: RE: Mutual Coupling
Dear Omar, [quote userid="473568" url="~/cadence_technology_forums/f/custom-ic-design/46781/mutual-coupling/1369454"]Is there any solution for this problem, or as you mentioned that using S-Parameter , imported from EM-simulator, is the best solution for that problem?[/quote] You can certainly create a circuit model using ideal elements from the analogLib to attempt to model the coupling between two distinct inductors. As I mentioned previously, you can also create a veriloga model that can model mutual inductive coupling. However, I personally am not aware of "component" means to include inductive coupling between two discrete inductors placed in a schematic. Shawn
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Forum Post: Monte Carlo Error when simulating larger array (smaller array runs just fine)
I have an array of 64 by 64 simple cells, the cells consist of no more than 10 transistors and their output is either VDD or GND (with mismatch). My problem is when I simulate for 64 rows (with each row consisting of 64 cells), Monte-Carlo throws up an error shown here: Interestingly when I run for fewer rows, for example 32 rows, Monte-carlo runs fine and I get the expected results. I am not exactly sure what the problem is so would appreciate any help. Thanks.
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Forum Post: When to ideally run an UNR Analysis?
Cadence recommend running the UNR analysis when your code coverage metrics are near 70-95% depending on the size of the design. RTL and code coverage data are inputs to the formal tool for UNR analysis. Provided RTL is frozen and the test suite is maturing I believe that the better the code coverage metrics are given as input, we get two advantages 1. Faster UNR analysis 2. Accurate UNR analysis. Some folks say that the UNR output shall not change if RTL is stable. I see i get more accurate UNR (Lower numbers), when I do the analysis when my test suite is mature enough to give good code coverage result. Kindly share your experiences if you see more accurate result when code coverage data is better. Thanks in Advance.
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Forum Post: RE: Monte Carlo Error when simulating larger array (smaller array runs just fine)
The only report of this specific error I've seen is when using the scaled-sigma sampling mechanism for high-sigma yield mode in ADE, and that was with an internal case. Without knowing the specifics of your technology or the models, it's hard to know what the problem is. Please contact customer support . Regards, Andrew.
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Forum Post: RE: Shift3 bindkey not working
Have you tried using the Options->Bindkey editor, picking the application that you are trying to enter a bind key for, and then using the green "+" button to add a bind key. Then in the place where it says "type new bind key" (or double click on the bind key cell on an existing row) press shift+3 on your keyboard (try a few other key combinations too to make sure it's working if this doesn't work). It should show you the bindkey incantation for your keyboard. For example, for me it says " sterling" (yes, shift-3 is £ on my keyboard as I'm in the UK with a UK keyboard). Andrew.
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Forum Post: RE: can't evaluate value of a tran signal at derived value
Hi andrew, thank you very much for your answer. I actually found out myself :) !!! I came back here to write the solution but already you already did !! Once again thank you. Olivier
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Forum Post: generate histogram from multiple run automatically
Hi there, I need to run multiple times, with different setups the same simulation and plot the histogram of a measurement from these simulations. It's almost like a "monte-carlo' like simulation but it's a tran-noise simulation. The simulation is the one described in this post : https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/46773/can-t-evaluate-value-of-a-tran-signal-at-derived-value I run the same simulation multiple times using a "dummy" variable. By dummy I mean the variable does not affect a circuit parameter. At the end of this multiple runs I'd like to automatically plot the histogram of the value I measure, in this case : time_read_t = cross(VT("/read") 1.65 1 "falling" nil nil nil) value_read = value(VT("/vout") time_read_t) Is there a way to plot this histogram ? Thank you very much for your help. Olivier
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Forum Post: Error in PSS and PNoise simulation of a VCO followed by Frequency detector with 150MHz clock signal
Hello I am facing difficulty in simulating phase noise of an oscillator circuit. The circuit consists of a Current starved VCO (2.4GHz) followed by a frequency sensor circuit. To the frequency sensor circuit I have given a 150 MHz clock frequency(reference). while running the PSS analysis it is showing an error that this is not an autonomous circuit instead it is a driven circuit because of that reference clock signal. After going through some forum I tried the PSS analysis with the oscillator mode unchecked and tstab as 800ns. but in this case it is not converging at all. Kindly guide me as i am stuck at this point. Thanks & Regards, Jayanta
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Forum Post: RE: generate histogram from multiple run automatically
Hi Olivier, In my case where I replicated (to some extent) your setup, my value_read is called sinVal (but the expression matches yours). I'm sweeping a variable (dummySeed) which I then use as the value of the seed on the transient noise options form (using VAR("dummySeed"). I then swept that from 1 to 100 (1:1:100) and I get a plot of the value read at the read time versus the sweep. If you then select that trace, and then in the ViVA graph do Measurements->Histogram. Pick the number of bins you want (I picked 10) and any other special options you like and set the Plot Mode to (say) New Subwindow. Hit Plot. You'll then get the histogram. In order to get this every time, I then selected the histogram (in the legend, say) and did Right Mouse->Send To->ADE. This adds a new expression into your ADE outputs. In Assembler, change the "Eval Type" column for that output to be "sweeps" (rather than "point") so that the histogram is computed across the sweep (note, in ADE Explorer the Eval Type column isn't shown by default - you have to go to the column headings in the Outputs pane and do Right Mouse and enable the Eval Type column). Here's my setup (ADE will change the colour of the output to indicate that it's not a "point" expression): Here's what I get from the plot after simulation: Hope that helps! Regards, Andrew.
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Forum Post: RE: ERROR ADEXL 7514
Hi Andrew, thanks for your feedback. I am trying to change .cshrc to use the IC618. However, after update to IC1618, i could only insert layout instance once, after that some error is reported in the CIW as below. Do you know what is the reason?
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Forum Post: RE: Error in PSS and PNoise simulation of a VCO followed by Frequency detector with 150MHz clock signal
Jayanta, You cannot simulate using PSS a circuit that has both a driven frequency and an autonomous frequency at the same time. This is because PSS requires a single fundamental frequency to be found which is the common frequency of all frequencies in the circuit - in other words, across the lowest common frequency. This is true with PSS whether you are using shooting or harmonic balance because everything is solved across the fundamental found. If you have an autonomous frequency and a driven frequency, the common frequency is chaotic - a very tiny change to the autonomous frequency can lead to a huge change in common frequency and so it cannot be solved (this is not just a matter of a software limitation; it's a fundamental restriction of the algorithms used). The harmonic balance analysis does however allow for having two tones setup (this is if you use the hb analysis) where the first tone is your autonomous signal (oscillator) and the second is the driven signal. The analysis will first try to converge with just the oscillator enabled (i.e. the driven signal not present) and then apply the driven signal - so the circuit must operate even without your 150MHz clock not present. I'm not sure semi-autonomous hb is really well-suited to this because I'm assuming your current starved VCO is a ring oscillator and hence fairly square, plus your lower frequency clock being square, so you'll need a fair number of harmonics of each. It may make more sense to contact customer support so that we can see more details of your actual circuit and what you're trying to simulate. Regards, Andrew.
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Forum Post: RE: ERROR ADEXL 7514
Can you please enter the following in the CIW: _stacktrace=50 sstatus(errsetTrace t) and then repeat the error? Ideally paste the resulting stack trace here rather than just a screenshot (it was hard for me to see that this was really gevPl and not gevPI). Also, which exact IC6.1.8 sub-version are you using? Typing getVersion(t) in the CIW will tell you that. I've found where it's used in the code, but I'd be surprised if that's the reason because it suggests that it doesn't know the cellView if that's the case. However, there's an article which uses a similar expression so it might be a consequence of something in your PDK. The stack trace will help me pinpoint that. Andrew.
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Forum Post: RE: ERROR ADEXL 7514
Hi Andrew, this is new CIW info, i think the issue still exist. my version is IC6.1.8-64b.500.2 _stacktrace=50 50 sstatus(errsetTrace t) t *Error* fprintf/sprintf: format spec. incompatible with data - "Format is 'gevPl%s%s%sCDFForm', argument #1 is nil" >> (... in CCSFormInitProc ...) (... in MOSFetFormInitProc ...) (... in unknown ...) (... in formInitProc ...) (... in uifAppendParamFields ...) (... in leiUpdateInstFormParamFields ...) (... in leHiCreateInst ...) leHiCreateInst()
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Forum Post: RMB Customize Enable Single Click Execution
This is enabled by default and is painful to me. How can I disable this by default?
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Forum Post: Integration with version control system
Hello everyone. I have been using OrCAD for more than a year now and I think about implementation a version control system. So far, I have used gitlab for symbols and footprints and I didn't expect it to work so good. Although symbols are stored in binary files, Gitlab handles them with no problems. There is no issues with creating symbols, pushing and merging. No conflicts at all. Additionaly, I share the libraries with other co-workers. Everyone is capable of commit. That's a plus for Cadence. But how do you manage your schematic and layout files? Is it any way to do it? I have enough of creating a copy once an hour or more often. What's your experience in that topic? What do you think?
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Forum Post: RE: generate histogram from multiple run automatically
Hi Andrew, thank you very much for your help. This is something I did not know. Actually I've never even noticed you could change this parameter from point to sweep. This is a very useful thing I'll use a lot, for sure. Have a good day. Olivier
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