Which version Allegro? And which license level do you have? MVIA errors change depending on license...
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Forum Post: RE: Minimum Blind/Buried Via Gap (L1-L2 and L11-L12)
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Forum Post: User Defined Skill Function - Alias Waveform
Hello, I would like to create a function that performs ideal aliasing on the output waveform of a simulation (particularly output noise). In other words, I want all the nyquist bands within a specified frequency range to be folded down to the first nyquist zone. The best approach I could think of was to manually clip, shift, flip, and add the noise voltage within each nyquist band to each other. This works well, but high frequency aliasing requires a lot of equations. Here is the waveform calculator formula of several additions (up to fourth nyquist) for reference: (clip(Vno2 0 VAR("fnyq")) + rshift(flip(clip(Vno2 VAR("fnyq") (2 * VAR("fnyq")))) (2 * VAR("fnyq"))) + lshift(clip(Vno2 (2 * VAR("fnyq")) (3 * VAR ("fnyq"))) (2 * VAR("fnyq"))) + rshift(flip(clip(Vno2 (3 * VAR("fnyq")) (4 * VAR("fnyq")))) (4 * VAR("fnyq"))) where Vno2 = (getData("out" ?result "noise")**2) fnyq is defined in the design variables I have also linked my attempt at a custom SKILL function, but it does not run. I don't have much background with SKILL, so I could have some bad code, but I've tried to follow the documentation and available scripts as best as possible. I would appreciate it if someone could take a look at my code and help me debug it or present a better option. Thanks. ---------------------------------------------------------- abAliasSignal.il
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Forum Post: Can i make the design rule check blind to a specific layer?
I am incorporating a device (memrsitor) in my layout that is not defined in the kit. I was thinking of representing the device by a layer that is not used in my design. However, this layer will have its own design rules that are different from the ones I want to set for my memristor? So, I was thinking of using a layer that does not affect affect the DRC tool (the DRC does not show an error no matter where it is placed) or make the tool ignore the design rules for a specific layer and use that layer to represent the memristor. Is that even possible? Any thoughts on that issue will be appreciated.
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Forum Post: OrCAD simulation - Propagation delay of CMOS inverter
I need to get the characteristics of dynamic parameters of CMOS inverter ( tplh,tphl,tp ) and measure them from the graph. Inverter is induced by square pulse generator with frequency 200kHz and fill factor of 20%. Inverter is loaded with capacitance 100pF . Questions: I have drawn the schematics, but don't know how to set parameters of VPULSE generator properly (I set V1=0, V2=5, PW=0.2, PER=0.000005 ). Also, how to set simulation profile? In DC sweep, I set voltage source V3 as a sweep variable and also include time domain (transient). How to get UDD=f(t) characteristics and measure dynamic parameters of CMOS inverter?
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Forum Post: RE: OrCAD simulation - Propagation delay of CMOS inverter
Note: I am using Orcad Cature CIS Lite 16.6. version.
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Forum Post: RE: OrCAD simulation - Propagation delay of CMOS inverter
PW would be the Pulse Width and PER would be the Period, for repetition, so your numbers are a bit off. For a VPULSE, you also need to account for Delay, TD (can be 0), before the first "switch", Rise, TR and Fall, TF. You can also use the regular multipliers for values. V1 and V2 are OK, start with a PER of 5u and get PW, TR and TF within that value. TR and TF will need to be reasonably fast to get a measurement from your inverter but cannot be 0 and very small values may cause the circuit to not converge. See the pspcref.pdf in the doc\pspcref folder in the installation for the parametric reference, Independent Current and Voltage sources.
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Forum Post: Continuous Path/Routing with Varying Width
Hello, I am using version IC6.1.6-64b.500.11. In layout editor, I would like to create a continuous (metal) routing (or path) which consists of pieces with different width. When I create a routing by pressing "p", the width is the same for each sub-part of the continuous path. Would it be possible to have what I want? Many thanks in advance. Best regards, Can
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Forum Post: unexpected dialogue box appear while simulation in pspice.
Hello, why this dialogue box is appearing while simulation. before some time everything was ok,i was able to see the black window where marker probe signal is displaying Regards DC
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Forum Post: RE: Select cell view from lib manager
Hi Lawrence, Thank you for your answer. I don't want to bother all of you with my questions, but I have another problem. I have a text field which allows the user to enter "letters, numbers and the characters . _-" . I've done this using, as suggested by Andrew, the ?modifyCallback option. The default value for that text box is "File Name", but if you try to delete that in order to enter your own text, it will delete all the characters and leave one in the textbox, which cannot be deleted. For eg., if you try to delete all characters either "F" or "e" will remain there. Can you figure out what's wrong please ? Best regards, Jose fileName = hiCreateStringField( ?name 'fileName ?prompt "Summary file :" ?value "File name" ?editable t ?defValue "test.txt" ;?default "test.txt" ;?callback "ddsUpdateSyncWithForm( )" ?modifyCallback "cb_filterUserInput" ?invisible t ; this parameter will be set back to nil later in the code ) ;============================================================================== ;===========cb_filterUserInput-"filter characters entered by the user" ======== ;============================================================================== procedure(cb_filterUserInput(a b c) let((retValue regexOut) unless(getchar(b strlen(b))==nil regexOut=rexMatchp("^[A-Za-z0-9_.-]" getchar(b strlen(b))) ; don't allow any character besides alphabet _ . and - ) ; end unless if(regexOut==nil then retValue=substring(b 1 strlen(b)-1) else retValue=b ); end if ); end let );end procedure
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Forum Post: RE: unexpected dialogue box appear while simulation in pspice.
Hard to be precise from a picture and no details, but I suspect that the circuit may have failed to converge. In the Simulation profile, Options tab, left-click on AutoConverge and enable the AutoConverge default options. You don't mention which exact version you are running, that could be a factor if you are not running the latest version. If the AutoConverge doesn't help, select the DSN file in the Capture Project Manager window and use File>Archive Project to create a single file (zip) archive of the project and attach it to your post for examination of the actual data and settings being used.
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Forum Post: RE: Minimum Blind/Buried Via Gap (L1-L2 and L11-L12)
You might need to set the BBVIA_SEPARATION, Drawing level property, Edit>Properties, set the Find drop-down to Drawing and More to get to the properties. By default "infinite" layers are considered for BB Via separation, try setting a value of 2 (for adjacent layers only) for BBVIA_SEPARATION, and the DRC for Top / Bottom BB Vias should be gone.
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Forum Post: RE: Select cell view from lib manager
The problem is because if the string is empty, you end up never setting regexOut so it has its default value of nil. Because of that, you end up in the substring branch of the final if, which will return nil - and because it returns nil, the original string is left unchanged. The solution is to change the let in the modify callback to: let((retValue (regexOut t)) However, I'm not sure I'd do it this way, because if you click part way through the string and type one of these illegal characters, it will get accepted - your code only deals with characters at the end. I would probably do it this way: cb_filterUserInput.badChars=pcreCompile("[^\\w.-]") procedure(cb_filterUserInput(a b c) pcreReplace(cb_filterUserInput.badChars b "" 0) ) For details on the regular expression, see "man perlre". All it means is any character that is not alphanumeric+_ (that's the \\w) or dot or hyphen. Regards, Andrew.
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Forum Post: Connecting SPICE ports inside a SystemVerilog-only testbench
Dear all, I'm trying to setup a mixed-signal simulation using SystemVerilog RNM and a transistor-level Spectre netlist for an analog block. I know that Verilog-AMS wreal nets can directly drive SPICE ports. Indeed, I want to use SystemVerilog-only constructs in my testbench, without the usage of Verilog-AMS constructs. However a direct connection between a real number and a SPICE port in not allowed since real is a discrete quantity. Does SystemVerilog allow to do this?
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Forum Post: RE: Continuous Path/Routing with Varying Width
Hi Can, I can do this by starting the wire, clicking where I want the width to change and then hitting F3 to bring up the options form and changing the width (which affects the new segment) clicking again, and so on. So I get: Is that the kind of thing you're after? I was trying in IC6.1.6.500.14 but it also works in IC617 ISR9 too (I think it's pretty likely it would work in ISR11 that you're using). Regards, Andrew.
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Forum Post: RE: Make a copy of the Kit
Why not just use an incremental technology database rather than a copy of the kit? That's exactly the kind of thing it's used for. So, create yourself a library and rather than "attaching" it to your technology library, use the "reference" choice instead. Having done that, you can use Tools->Technology File Manager in the CIW to Dump the technology file for your library; you'll see that it contains just a controls section with a reference library specified. You can then add your own layer definitions (for the additional layers) into this ASCII technology file - for example syntax see /tools/dfII/samples/techfile - there are several files in there. Define just the techLayers section within layerDefinitions for the layers you want, plus the techDisplays section to define the Layer Purpose pairs you want, and how they would be rendered. Of course, you can add constraints etc for these additional LPPs if you need them. Doing this means that your original kit is unaffected, but you've "topped up" the technology with your additional information. Anyone else could then attach to your new library and pick up the compound (incremental) technology database. Regards, Andrew.
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Forum Post: RE: User Defined Skill Function - Alias Waveform
A few things: I'd probably avoid using the prefix "ab" as it tends to mean that people see the code and think it came from me (which it didn't here). Use your own initials or a unique prefix for your company. You could potentially do this using a "sampled" pnoise analysis which inserts an ideal sampler in the output of the circuit which would cause the noise to be aliased. There were a few things that were wrong - you had some parts of the code referencing the wrong waveform, you were using sum() - which isn't a function, and there were odd mistakes here and there. Anyway, I rewrote the code in C-style (probably easier to read if you're not familiar with LISP) and corrected it. I think this is OK now... /*************************************************************** * * * (abAliasSignal waveform fsample fmin fmax) * * * * Given a waveform, a sampling freq, and freq range compute * * the aliased signal. * * * ***************************************************************/ procedure(abAliasSignal(waveform fsample fmin fmax) cond( ;--------------------------------------------------------------------- ; Handle ordinary waveform ;--------------------------------------------------------------------- (drIsWaveform(waveform) let((len lastX sourceYVec xVec yVec clippedwave (result 0) resultnew nmax) ;------------------------------------------------------------------ ; Clip the signal and alias the signal in the range specified ;------------------------------------------------------------------ clippedwave=clip(waveform fmin fmax) xVec=drGetWaveformXVec(clippedwave) len=drVectorLength(xVec) lastX=drGetElem(xVec sub1(len)) ; Find the maximum nyquist sideband nmax=floor(lastX/(fsample/2.0)) ; Sum all of the signal of the clipped waveform into 1st nyquist for(n 0 nmax-1 resultnew= if(oddp(n) then rshift(flip(clip(clippedwave n*fsample/2 (n+1)*fsample/2)) (n+1)*fsample/2) else lshift(clip(clippedwave n*fsample/2 (n+1)*fsample/2) n*fsample/2) ) result=result+resultnew ) ;------------------------------------------------------------------ ; Copy units and axis name across from source waveform ;------------------------------------------------------------------ sourceYVec=drGetWaveformYVec(waveform) yVec=drGetWaveformYVec(result) yVec->units=sourceYVec->units yVec->name=sourceYVec->name result ) ) ; waveform ;--------------------------------------------------------------------- ; Handle family ;--------------------------------------------------------------------- (famIsFamily(waveform) famMap('abAliasSignal waveform fsample fmin fmax) ) ; family (t error("abAliasSignal - can't handle %L\n" waveform) ) ) ; cond ) Regards, Andrew.
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Forum Post: RE: Can i make the design rule check blind to a specific layer?
This probably depends on whether you can (or want) to modify the DRC rule deck. If you draw everything on layers the DRC rules know nothing about, you probably don't have to do very much - see your other post Make a copy of the Kit Regards, Andrew.
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Forum Post: RE: ADE XL without UI
That won't work, because the db functions are for loading OpenAccess databases, not ADE XL databases. This is actually a whole lot easier in ADE Assembler and Explorer in IC617 because you can use maeLoadSetup() and then maeRun() - really easy. In ADE XL though, you could either save the setup within the ADE XL view to a setup state and then use this kind of methodology: ;----------------- Setup State "corner sims" --------------- ocnSetXLMode() ocnxlTargetCellView( "opamp090" "full_diff_opamp" "adexl" ) ocnxlProjectDir( "./simulation" ) ocnxlResultsLocation( "" ) ocnxlSimResultsLocation( "" ) ocnxlLoadSetupState( "corner sims" 'retain ?tests t ?vars t ?parameters t ?currentMode t ?specs t ?corners t ?extensions t ?runOptions nil ?wavespecs nil ?modelGroups nil ?relxanalysis nil ?checksasserts nil ) ;====================== Job setup ============================================== ocnxlJobSetup( '( "blockemail" "1" "configuretimeout" "300" "distributionmethod" "Local" "lingertimeout" "300" "maxjobs" "1" "name" "ADE XL Default" "preemptivestart" "1" "reconfigureimmediately" "1" "runtimeout" "-1" "showerrorwhenretrying" "1" "showoutputlogerror" "0" "startmaxjobsimmed" "1" "starttimeout" "300" "usesameprocess" "1" ) ) ocnxlRun() ocnxlOutputSummary() ocnxlEndXLMode() This is using OCEAN XL to do the job, but you have to use the ocnxlLoadSetupState function - there's no function to load the active setup, rather oddly. Or you could use this: axlSess=axlCreateSession(getCurrentTime()) axlSetMainSetupDBLCV(axlSess "opamp090" "full_diff_opamp" "adexl") axlRunSimulation(?session axlSess ?callback "exit()") Regards, Andrew.
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Forum Post: RE: User Defined Skill Function - Alias Waveform
Thanks for the fixes, Andrew. I will also give the pnoise option a try. I thought the "ab" was for your initials, but I wasn't sure - I will remove that from the code and update the file later. -- I can follow your code and everything looks good to me, but when I click on the function in the calculator, no form appears. Did you see anything wrong in the rest of the code?
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Forum Post: RE: User Defined Skill Function - Alias Waveform
Hi Michael, Before I look at that, which IC version are you using? There is an easier way in IC617 which means you don't have to write the form code... Regards, Andrew.
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