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Forum Post: RE: Eagle to Allegro Conversion

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This sounds like you have an old binary, not XML, formatted Eagle file, the translator needs the later XML format.

Forum Post: RE: Eagle to Allegro Conversion

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Do you mean, that the .brd files are formatted in XML format and I need an updated .brd file ? I am fetching the .brd files form this link github.com/.../MOD-WIFI-ESP8266-DEV all the .brd files show the same error Thanks Abhishek

Forum Post: RE: pspice error-undefined float property

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The pins on the Schematic part don't have any property to determine what behaviour should be assumed for floating, unconnected pins, in the simulation. You could connect the pins, a 1G resistor to 0 on each could work, or add FLOAT properties to the Pins, values for FLOAT are: ERROR, the default; RtoGND, assume a resistor; UniqueNet, available to Probe.

Forum Post: RE: Eagle to Allegro Conversion

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Eagle v6.5, and later, uses XML format, this (binary) format file needs to be opened and saved with Eagle v6.5, or later, to get the data into XML format for conversion.

Forum Post: error in pspice simulation

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Hello, someone help me to resolve the error. --------------- INFO(ORPROBE-3209): Simulation Profile: 0-BlockDiagram-sasa simulation try 2 --------------- INFO(ORPROBE-3183): Simulation running... ** Profile: "0-BlockDiagram-sasa simulation try 2" [ d:\dc workspace\sasa project simulation\try2\orcad design 170104\sasa_iii_hard Reading and checking circuit Circuit read in and checked, no errors Calculating bias point for Transient Analysis Starting GMIN stepping Starting power supply stepping Starting pseudo-transient algorithm ERROR(ORPSIM-16550): Floating point computation failed during matrix solution. Possible solutions: 1)Ensure that all device parameters are in valid range. 2)Try using .options LIMIT Divide by Zero, Divide INTERNAL ERROR -- Divide by Zero, Divide Run aborted Total job time (using Solver 1) = 14.43 INFO(ORPROBE-3188): Simulation aborted Regards DC

Forum Post: RE: error in pspice simulation

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Which exact version are you running? (Check from Help>About) It is possible that you may have invoked an internal error which has been addressed in a hotfix but may be more likely that you have an invalid model, or parameters, which result in a "divide by zero" on a value and subsequent termination of the simulation. If you want to archive the project and attach it, you data could be analysed, otherwise you would need to contact your supplier, either a Cadence Channel Partner, or Cadence direct, for support.

Forum Post: viewing spectre simulation results right from the start

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Hi to everyone! We're looking for a solution for an apparently simple problem. When starting a simulation with spectre, we want to look into the results right from the beginning. We want to do this to evaluate the simulation immediately. This is sometimes necessary for long-lasting simulations to stop them if they are going into the wrong direction. However, spectre seems to update the saved simulation data periodically in fixed time frames. Thus, for long simulations we have to wait for a very long time to be able to take a first look at our saved outputs. Is there a command or a flag for spectre (MMSIM) that I can set to shorten this time frame? We spent a lot of time searching for this option in the Cadence manuals without success. We are using IC6.1.6 and MMSIM14.1 but the problem is version independent since older and newer releases show same behavior in our setup. Thank you for your help in advance.

Forum Post: RE: Select cell view from lib manager

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Hi Andrew, That didn't work for me. You see, when I hit the button "..." from the file selector, the box is filled incorrectly even if I remove the callback. Moreover the previous version didn't have this problem. As I couldn't find a way to attach files to this message, I've pasted the code below (I am sorry for that) . Thanks in advance. Best regards, Jose Version 0v5 (old one) ;============================================================================== ;=============== Display main Form - Create Main form" =================== ;============================================================================== procedure(createMainForm() let((label1 doneButton cellView1 cellView2 selectButton1 selectButton2 selectButton3 sep1 myToggle temp) ; template loading and saving ; Directory Select allows user to select the directory where to save the files dataPath = hiCreateFileSelectorField( ?name 'dataPath ?mode 'directoryOnly ?prompt "Save the file to: " ?value "Please enter the path" ?defValue "~/Desktop/scripts/scriptOutputs" ?callback "validateDataPath()" ?editable nil ?invisible t ) hiCreateAppForm( ?name 'settingsForm ?formTitle "Compare summary files" ?fields list( list(label1 10:10 600:0 40) list(sep1 0:35 600:0) list(cellView1 15:50 500:30 100) list(cellView2 15:85 500:30 100) list(selectButton1 520:50 50:30 30) list(selectButton2 520:85 50:30 30) list(selectButton3 120:120 90:30) list(myToggle 250:122 -1:-1) ; -1 indicates fields that aren't used, so they can take any value list(myToggle2 350:122 -1:-1) ; -1 indicates fields that aren't used, so they can take any value list(dataPath 15:120 500:30 100) list(fileName 15:155 250:30 100) ) ; end list ) ; create form hiDisplayForm(settingsForm) ; Display form ); end let ); end procedure ;============================================================================== ;============== validate data path "validateDataPath" ==================== ;============================================================================== procedure(validateDataPath() let((myRadio1 myRadio2 txtStr parsedStr retValue) myDirStr=settingsForm->dataPath->value if((myDirStr!="Please enter path") && (myDirStr!="") then myDirStr=simplifyFilename(myDirStr) ; Expands myDirStr path ; if the path entered by the user doesn't end with "/" add it to the path unless(substring(myDirStr strlen(myDirStr))=="/" myDirStr=strcat(myDirStr "/") ) printf("\n myDirStr -> %s \n" myDirStr) if(isDir(myDirStr)==t then printf("Valid dir!\n") settingsForm->dataPath->value=myDirStr retValue="t" else printf("That's not a Valid dir !\n") settingsForm->dataPath->value="" retValue="nil" ) ; End if else myDirStr="" ) ; end if retValDataPath=retValue ) ; End let ) ; End Procedure Version 0v6 (new one) procedure(createMainForm() let((label1 doneButton cellView1 cellView2 selectButton1 selectButton2 selectButton3 sep1 myToggle temp) ; Directory Select allows user to select the directory where to save the files dataPath = hiCreateFileSelectorField( ?name 'dataPath ?mode 'directoryOnly ?prompt "Save the file to: " ?value "Please enter the path" ?defValue "~/Desktop/scripts/scriptOutputs" ?callback "validateDataPath()" ?editable nil ?invisible t ) hiCreateAppForm( ?name 'settingsForm ?formTitle "Compare summary files" ?fields list( list(label1 10:10 600:0 40) list(sep1 0:35 600:0) list(cellView1 15:50 500:30 100) list(cellView2 15:85 500:30 100) list(selectButton1 520:50 50:30 30) list(selectButton2 520:85 50:30 30) list(selectButton3 120:120 90:30) list(myToggle 250:122 -1:-1) ; -1 indicates fields that aren't used, so they can take any value list(myToggle2 350:122 -1:-1) ; -1 indicates fields that aren't used, so they can take any value list(dataPath 15:120 500:30 100) list(fileName 15:155 250:30 100) ) ; end list ) ; create form hiDisplayForm(settingsForm) ; Display form ); end let ); end procedure ;============================================================================== ;============== validate data path "validateDataPath" ==================== ;============================================================================== procedure(validateDataPath() let((myRadio1 myRadio2 txtStr parsedStr retValue myDirStr) myDirStr=settingsForm->dataPath->value if((myDirStr!="Please enter the path") && (myDirStr!="") then myDirStr=simplifyFilename(myDirStr) ; Expands myDirStr path ; if the path entered by the user doesn't end with "/" add it to the path unless(substring(myDirStr strlen(myDirStr))=="/" myDirStr=strcat(myDirStr "/") ) printf("\n myDirStr -> %s \n" myDirStr) ;if(isDir(myDirStr)==t then if((isDir(myDirStr)==t) && (isWritable(myDirStr)==t) then printf("Valid dir!\n") settingsForm->dataPath->value=myDirStr retValue="t" else printf("That's not a Valid dir or you don't have write permissions!\n") dispMessage("That's not a Valid dir or you don't have write permissions!\n") ;settingsForm->dataPath->value="" retValue="nil" ) ; End if else myDirStr="" ) ; end if retValDataPath=retValue ) ; End let ) ; End Procedure

Forum Post: RE: How to get status of variable (enabled/disabled) from checkpoint using SKILL

Forum Post: RE: Select cell view from lib manager

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Jose, You should be able to attach files via the rich text formatting interface (there's a little Insert/Edit Media icon). However, I have seen this break sometimes... (I've not checked today). I just checked your code. The reason why the new code breaks and the old code works is that your validateDataPath() function uses simplifyFilename() to resolve the relative path to a full path (in both cases). However, in the new version, it checks: if((isDir(myDirStr)==t) && (isWritable(myDirStr)==t) then printf("Valid dir!\n") settingsForm->dataPath->value=myDirStr ... In other words, it only updates the dataPath on the form if the path is a directory and it's writable. In the old version it didn't check whether it was writable. The settingsForm->dataPath->value=myDirStr is setting it to the simplified filename, and hence resolving the ../../../ etc. If in the new code I add: dataPath->hiSimplifyFilename=t immediately before the hiCreateAppForm() call - i.e. after you've created the field and stored it in the dataPath variable (which doesn't appear to be local, by the way; I assume that's an oversight), then it also solves the problem because the simplifyFilename is done at source regardless of what you do in your callback. Regards, Andrew.

Forum Post: Harmonic Balance -LC Oscillator

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Hi all, I am facing a weird issue. When I am simulating a LC Oscillator in HB, the Estimated oscillating frequency from Tstab Tran differs around 1GHz from the calculated fundamental frequency. The oscillator aims to oscillate in 11.5Ghz. When I am saying "Estimated oscillating frequency from Tstab", I am referring to the frequency that SpectreRF simulator calculates after the simulation is done. It's written in the output log file. I have followed all the recommended settings that MMSIM 14.1 Spectre RF document proposes, such as: A] Transient-Aided Options: 1) Run Transient -->either YES or Decide automatically 2) Detect Steady State -->YES 3) tstab= 30n B] Fundamental Freq =12G Number of Harmonics =12 Over-sample Factor = 12 C] Accuracy: conservative D] Options button: 1)Integration method tstab: I tried both traponly and trap. I am getting the same freq. deviation 2)maxstep=1psec,350f --> I am getting the same freq. deviation From my previous experience, the estimated osc. frequency from tstab tran is a bit close to the fundamental freq. My questions are: 1) Could anybody tell me what is the reason behind this big deviation? Am I doing something wrong? 2) Is it safe to run the same testbench in Transient analysis and set the stop time around 200nsec and then measure the frequency using the "freq" function from the calculator menu? Thanks in advance

Forum Post: ADE XL and virtuoso -nograph not working

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On trying to run any simulation in ADEXL I am getting ADEXL 1921 error (failed to start job after 3 attempts. Possible reasons could be ........). Also on trying to execute virtuoso -nograph I am getting the following error: "Xlib: connection to "servername:80.0"refused by server Xlib: No protocol specified *WARNING* Could not open display servername: 80. If no server is running for this display, please remove the file /tmp/.X11-unix/X80/ Trying another display ........................ *WARNING* unable to connect to a non graphical X Window Display server. My version is IC6.1.5-64b.500.15. ADEXL was working earlier for me and still does for other users in our server. The issue is only with my account apparently. I tried running virtuoso from a new folder using some basic cdsenv cdsinit files as well. I can start up the virtuoso GUI using virtuoso & and the normal ADE runs just fine. We ssh into the server with X11 forwarding. Any ideas regarding what changed and how could I rectify this issue?

Forum Post: RE: Creating digital buses in ADE XL: awvCreateBus

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Unfortunately I am working in a University environment, and I am not sure if moving to IC617 would be possible. I am working with IC6.1.6.500.14. I will maybe export my waveform data and plot the result and analyze using Python.

Forum Post: How to write the same function in IC 5.1 which dbGetHierPathTransform in IC 6.1 ?

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Hi All, I want to copy lower hierarchy level of label to top level , I saw a source link "SKILL script to copy lower level labels to the top level" , It can work in IC 6.1 ,But I need to do in IC 5.1 , IC 5.1 no dbGetHierPathTransform => undefined variable ... How to let the code work in both IC 5.1 & IC 6.1 ? Thank you, Charley

Forum Post: Problem with Hidden states in Verilog A while running PSS/PAC...

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Dear All, I wrote a code in Verilog A to generate four different clocks clk1, clk2, clk3 and clk4 from clk, as shown below. These clocks are used for switching in the filter. While doing PSS/PAC analysis for plotting the magnitude response of filter, its giving an error shown below, Could anybody please tell how can I avoid this. I am a beginner in Verilog A, the code is also posted for the reference. Regards, Jayaram ERROR In Running PSS/PAC... Error found by spectre during periodic steady state analysis `pss'. ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'JYR_CLKgen_VerA'. Skipped. /home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 18: Hidden state variable: count /home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 19: Hidden state variable: vout1 /home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 19: Hidden state variable: vout2 /home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 19: Hidden state variable: vout3 /home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 19: Hidden state variable: vout4 Analysis `pss' was terminated prematurely due to an error. CODE: `include "constants.h" `include "disciplines.h" module JYR_CLKgen_VerA(vclk, vclk1, vclk2, vclk3, vclk4); input vclk; output vclk1, vclk2, vclk3, vclk4; electrical vclk, vclk1, vclk2, vclk3, vclk4; parameter real vtrans_clk=0.9; parameter real voh=1.8; parameter real vol=0.0; parameter real tdel = 0 from [0:inf); parameter real trise = 0.1n from [0:inf); parameter real tfall = 0.1n from [0:inf); integer count; real vout1, vout2, vout3, vout4; analog begin @(initial_step) begin count = 0; end @ (cross(V(vclk) - vtrans_clk, 1.0)) begin if (count == 0) begin vout1 = voh; vout2 = vol; vout3 = vol; vout4 = vol; end else if (count <= 7) begin vout1 =vol; vout2 = voh; vout3 = vol; vout4 = vol; end else if (count <= 20) begin vout1 = vol; vout2 = vol; vout3 = voh; vout4 = vol; end else if (count <= 31) begin vout1 = vol; vout2 = vol; vout3 = vol; vout4 = voh; end if (count<=31) count = count+1; else count = 0; end V(vclk1) <+ transition(vout1,tdel,trise,tfall); V(vclk2) <+ transition(vout2,tdel,trise,tfall); V(vclk3) <+ transition(vout3,tdel,trise,tfall); V(vclk4) <+ transition(vout4,tdel,trise,tfall); end endmodule

Forum Post: RE: How to write the same function in IC 5.1 which dbGetHierPathTransform in IC 6.1 ?

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Hi Charley, See my code which I posted in response to this earlier post: Regards, Andrew.

Forum Post: RE: Problem with Hidden states in Verilog A while running PSS/PAC...

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This is not entirely trivial to avoid because of the fact that you are storing state in the count and vout1->4 variables. I'd advise you to look at this page: In particular the Hidden state in SpectreRF application note. I posted the link to the page rather than the document directly so you could also easily find the Verilog-A models that Ken Kundert uses in his app note. Regards, Andrew.

Forum Post: RE: error in pspice simulation

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hii, problem solved with auto convergence!! thanks

Forum Post: RE: How to write the same function in IC 5.1 which dbGetHierPathTransform in IC 6.1 ?

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Hi Andrew, Thank you,I will study & try it. PS: How do I copy & paste the text to a new file will keep the same(has return line) ? Charley

Forum Post: RE: How to write the same function in IC 5.1 which dbGetHierPathTransform in IC 6.1 ?

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Hi Andrew, I cnage the browser from Firefox to IE , It can do it. Charley
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