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Forum Post: RE: How to write the same function in IC 5.1 which dbGetHierPathTransform in IC 6.1 ?

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Hi Andrew , Yes, It work. The function can do it. Thank you, Charley

Forum Post: Problem with Monte Carlo in ADE XL: no psf written

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Hi, I am new to ADE XL and want to run a MC sim bt it behaves weird and I cannot see/browse the results. I am not sure if I am doing anything wrong or if it is buggy. I am ADE L user so I describe what I did: 1. Set up my environment in ADE L as usual. Simple transient sim with output waveform as result 2. Start ADE XL, create new cell, Tests -> Click to add test and then load the state from ADE L. The Outputs Setup and Results get populated. 3. I am working with an ST PDK, so I go to ArtistKit -> Load corners from state and select the scenario that I previously saved where I enabled statistics/monte cartlo. I choose "Select Nominal Corner: yes" and "Location: ADE-XL Results Database" 4. "Corners" in the data view gets populated with my monte carlo states. I think this is fine. 5. I select "Single Run, Sweeps and Corners" and hit the "Plot all waveforms" button. IT WORKS -> the results browser shows two traces on top (one for nominal and one for monte carlo) 6. Then I select "Monte Carlo Sampling" and select number of points, save mismatch data etc and run. 7. After the run, hitting the "plot all waveforms" button, the window is just black and empty ! Hitting Results browser button also shows the empty results browser. It seems that no psf file is created which is there for the interactive run. The file adexl/data/MonteCarlo.0/psf/testlib:testcell:1/psf is empty. Opening the run log shows that all runs (total number of points 4, number of points passed 4) have been completed successfully. Am I doing anything wrong here? Where are the MC results supposed to be?

Forum Post: RE: Problem with Hidden states in Verilog A while running PSS/PAC...

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Thanks for the reply Andrew, I'll go through the document and Models... Regards, Jayaram

Forum Post: RE: Footprint Viewer not visible in 16.6

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I had a similar problem with the footprint not showing up. I did edit the .INI file in the C:\Cadence\SPB_16.X\tools\capture\capture.ini to point to our footprint folder. The problem still persisted after that because the location moved. Capture was now reading the capture.ini file from c:\Cadence_env\cdssetup\OrCAD_Capture\16.6.0\capture.ini. I updated the capture.ini file in the new location which fixed the problem.

Forum Post: RE: ADE XL without UI

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Hi Andrew, Thank you for the reply. I have found that the Ocean script with active setup can be saved directly from the ADEXL UI. I can modify this script to change the file paths and run the simulation with the "virtuoso -nograph" option. This way is exatly the same as running the ADEXL UI simulation except for the run name. But that doesn't make any difference to me. Thanks again for pointing me in the right direction, Eugene

Forum Post: Getting started

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I've been looking and can't find a "Getting Started" guide. Particularly, I'm looking for how I can set up, edit a use footprint libraries. I was able to find the library tool for Capture, but not for PCB Editor. I'm using Allegro 17.

Forum Post: RE: Getting started

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There's not a real "Getting Started" guide but the actual manual. Under Help->Documentation, open the Allegro User guide and there is a section dedicated to library development. Also, some YouTube vids exist as well as some guides floating around the web... If you get stuck, write back

Forum Post: Setup RAVEL

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Hi Guys, I couldn't run RAVEL under Allegro PCB Designer Manufacture tab. It prompted "Environment Variable DFM_RAV_PATH is not set. Please set it to the correct path and try again." Please let me know how. Thanks! ;-)

Forum Post: RE: Setup RAVEL

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Hi, Please set your DFM_RAV_PATH to c:/cadence/spb_17.2/share/pcb/dfm_ravel or c:/cadence/spb_16.6/share/pcb/dfm_ravel (based on where your Cadence installation folder is) and try again. Thanks, Bindu

Forum Post: RE: Setup RAVEL

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Hi Bindu, where and how can I set the DFM_RAV_PATH?

Forum Post: RE: Setup RAVEL

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Please type the following in your Allegro Command Window (assuming you are using Allegro 17.2 and Cadence installation directory is c:/cadence): set dfm-rav_path c:/cadence/spb_17.2/share/pcb/dfm_ravel Thanks, Bindu

Forum Post: RE: Setup RAVEL

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Correction: Please type setup dfm_rav_path c:/cadence/spb_17.2/share/pcb/dfm_ravel

Forum Post: RE: Setup RAVEL

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Oh yeah, i checked my env and the DFM_RAV_PATH wasn't called. I had used an old file. Thanks again. ;-)

Forum Post: Function to detect if a given bBox is entirely covered by metal

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Hi, any existing functions which is able to detect if a given bBox (on a given visible layer) is entirely covered by metal (can be Via pad, pin pad, shape, clines)? e.g given a bBox, the function can detect the voids within the bBox and return a nil, else return a t. if not, any existing basic function that i can start with to write such a function?

Forum Post: How to use axlSpreadsheetDefineCell

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How to use axlSpreadsheetDefineCell to formula = d1 + e1, i use axlSpreadsheetDefineCell (1 5 "green" "String" "= d1 + d1") string can be written but the formula can not be enabled

Forum Post: Allegro Design Entry-DRC-Check Power Ground Mismatch Query

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Hi, Please find below my query regarding DRC check in the Allegro Design Entry CIS 16.6, Please help to clarify, Example#1: If power pin (Eg. GND1) connected to different GND net (Eg. AGND) then I'm getting below Question in DRC Check, INFO(ORCAP-2212): Check Power Ground Mismatch QUESTION(ORCAP-1589): Net has two or more aliases - possible short? U1,GND1 GND1 AGND Schematic, Page 03 (8.40, 9.30) Expectation based on Example#1: but if the Power Pin (Eg. GND1) mistakenly connected to different signal Net (Eg. ENABLE) instead of power Net, why not the tool (Allegro Design Entry 16.6) show similar question !!?? I expect below question but tool not showing it in the DRC check result !! (is it only checking within Power pins ??!!) INFO(ORCAP-2212): Check Power Ground Mismatch QUESTION(ORCAP-1589): Net has two or more aliases - possible short? U1,GND1 GND1 ENABLE Schematic, Page 03 (8.40, 9.30) Is there any option to find & fix this mistaken connection on the DRC checking ??!! (I think one option is to configure ERC matrix but would like to know is there any other option!!) Thanks for your support & Clarification.. Thanks.

Forum Post: RE: Allegro Design Entry-DRC-Check Power Ground Mismatch Query

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This "Power Ground" DRC actually checks that the Pin Name assigned to Power Pins matches the Name of the Net that the Power Pins are connected to, for the vast majority of users, this DRC is of no use whatsoever. What you are looking for is "Report all net names", this reports multiple net aliases attached to nets as possible shorts - since the tool has no definitive knowledge of whether multiple aliases were intentional, or not, this is just a report for the user to investigate.

Forum Post: RE: Allegro Design Entry-DRC-Check Power Ground Mismatch Query

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Hi oldmouldy, Thanks for your prompt response & clarification.. Below is my case with actual circuit example, but DRC check do not show net has two or more alias..!! For Pin 4 DRC showing, (here i think tool assumes Net alias for pin same as pin name (GND2) & comparing with actual net name (GND) and showing mismatch) INFO(ORCAP-2212): Check Power Ground Mismatch QUESTION(ORCAP-1589): Net has two or more aliases - possible short? Y1,GND2 GND2 GND Schematic, Page 03 (8.40, 9.30) But Pin 2 as well is power pin but mistakenly connected to signal XTAL2 instead of GND but no where in the DRC I'm getting as below, Net has two or more aliases - possible short? Y1,GND1 GND XTAL2 Could you please help clarify DRC setting to identify this kind of manual error.. Thanks, Bala.

Forum Post: RE: Function to detect if a given bBox is entirely covered by metal

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There is no such existing function. You need to create a polygon as large as your bBox. Then get from each copper element the polygons (axlDBGetPad, axlDBGetShapes and then pull each shape through axlPolyFromDB) and then do an axlPolyOperation( bbox_poly list_of_cu_poly 'ANDNOT). This subtracts all CU poly's from the bbox poly. If any poly remains then you have voids. Perhaps you need also to do something with the voids in shapes, axlPolyFromHole. If you have many elements it is wise to do a pre-selection (axlAddSelectBox) of the via's, cline(segs) and shapes. Polygon operation can take some time if you pass a lot of items.

Forum Post: Breaking up large pin count connectors

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Hello, I am looking for a better way yo place large pin count connectors in capture. Presently I have always make a multi package part with the pins grouped in some way. This works OK, but sometimes the schematics would be more readable if I could arrange the pins differently, and I would prefer to not have to recreate new parts for each different arrangement. Is there a way to create a parts where each pin is a separate item that can me placed and moved as a single unit, and I can then just arrange the any way I wanted to? Even be able to have them in different locations on the sheet?
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