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Forum Post: searching FOR LIBRARY PARTS IN MULTIPLE SUBDIRECTORIES.

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I create my footprints in PCB Libraries footprint editor. I creates a subdirectory for each of my footprints. I have to copy the .DRA .PSM .TXT and .pad files from the subdirectories to the main directory. Is ther a way to have the software look in the library directory and all subdirectories ?

Forum Post: dbWriteSkill encounter : error close:error closing file

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hi, i am using the code: cvId=dbOpenCellViewByType("test" "otcind" "layout" "maskLayout") dbWriteSkill(cvId "/home/s01/a.il" "w" "4.4") to dump a graphical pcell skill code in IC616, when i run the first skill sentence: cvId=dbOpenCellViewByType("test" "otcind" "layout" "maskLayout") the feedback is OK. but when i run the second one: dbWriteSkill(cvId "/home/s01/a.il" "w" "4.4") the CIW feedback the following error: *Error* close: Error closing file I have check the path:/home/s01/a.il and its disk space is not full. This post ( support.cadence.com/.../ArticleAttachmentPortal ;pageName=ArticleContent&sq=005d0000005nekwAAA_201722416744619) says it has relation to the /tmp file. (I don't have access to the /tmp file.) Is it ture? and how can I solve this problem? thanks in advance!

Forum Post: RE: dbWriteSkill encounter : error close:error closing file

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That article is about the stream interface, and not dbWriteSkill - so it's not really relevant when talking about /tmp. I don't believe dbWriteSkill writes anywhere other than the path you specify - it writes two files if it's a pcell - the cellView dump, plus the pcell code. Both are in the same directory. I've found no reports of this. It might be that the disk isn't full, but maybe your quota is exceeded and so you can't write any more data? Errors during closing of files are pretty rare... the most likely situation is that when trying to flush the buffer and actually write to disk it can't because it's not allowed to write any more to the disk. Generally commands such as "quota -v" would tell you your quota situation - but it's probably best to check with your IT in case the quotas have been set up differently (if that's what it is). Regards, Andrew.

Forum Post: RE: ead_workshop - ade-xl error message (1921)

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Andrew, There are problems with EAD tool from adexl. We have the licenses required to use EAD. The tools are updated. The setup is correct. The problem is for adexl simulation with option: "Enable Electrical Data Capture for EAD Flow". We obtain the following message: INFO (ADEXL-2107): Job 23 timed out while pending after 300 seconds Timeouts are generally caused by a simulator nonconvergence or legitimate runtime. Timeout duration can be modified in the 'Job Policy Setup' dialog. For no timeout, enter nothing. First we think that the problem was the workshop mentioned before. But the same problem occur for different circuits. Could you help us? Thanks, Regards, Rafael

Forum Post: RE: searching FOR LIBRARY PARTS IN MULTIPLE SUBDIRECTORIES.

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Not directly as far as "in subdirectories too"...that would be awesome! I personally have the .DRA files all categorized in separate directories below the main library path but I put the .psm in the uppermost path. The other way to do this is to add each and every individual symbol path to the PSMPATH variable.

Forum Post: RE: Breaking up large pin count connectors

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Yes. You can make a single pin and then using heterogenous parts you can add as many as the pincount requires. Each pin is added separately to the schematic. Just stack the individual pieces together and make it look like one large connector... I can post some graphics if you need more ideas...

Forum Post: Tcl script, for library manipulation

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Hi all, I am trying to use CapLibPropUtil.tcl script in the tools/capture/tcl folder. But the parameters are vague. In the add property command the parameter "Olb path" is ok. But what is the "log file path"and "force" parameters..????. And also i tried to read the script andtcl guide but i didnt understand the concept. Can any also tell me what this command means "Set lstatus [Dbostate]" Dbostate means?. Hope helping hands :) Thanks in advance

Forum Post: RE: viewing spectre simulation results right from the start

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Hi Rene You can control the speed as which spectre flushes out psfxl data using the following variable: setenv CDS_PSFXL_INIT_FLUSH_INTERVAL 10 The above means that spectre will flush out the 1st set of data after 10 seconds instead of the default 300 seconds (5mins). Please refer to either COS article 11643554 or search for "FLUSH" in $CDSHOME/doc/anasimhelp/anasimhelp.pdf for more details. Best regards Quek

Forum Post: generate power grid library

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Hi, I have "qrcTechFile" file from foundry and I want to generate power grid library for dynamic power analysis but in "Set Power Library Mode" menu I don't know what's needed for "LEF-Tech Map" and how can I create a .map file. Please help me with that. Thanks in advance, Milad

Forum Post: 17.2 alias key problems

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In Version 17.2 my alias keys do not work until is use the middle mouse button to scroll. Once I move the mouse then my page-up and page-dwm keys zoom in and out. Is there a fix for this ?

Forum Post: No DRC errors with a via located in a non plated hole.

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I have a number of vias located close to a non plated hole and I do not get any errors. Even if I move A VIA insIde the hole AND I do not get any errors. I have all errors enabled. Any reason I do not get an error ?

Forum Post: Closing the view file through SKILL

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Hello Folks, Is there a command in SKILL to close a log file which is already open and is displayed by command view( file_path ) ? Thanks, Jay

Forum Post: RE: Closing the view file through SKILL

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Jay, Do you mean to close the log file window? That would be hiCloseWindow(windowId) - e.g. hiCloseWindow(hiGetCurrentWIndow()) . Regards, Andrew.

Forum Post: RE: No DRC errors with a via located in a non plated hole.

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In constraint manager, go under "Analysis Modes" and make sure the highlighted box is checked. With it off, you won't get any DRC errors.

Forum Post: RE: Getting started

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There are several tutorials originally created for University students that can be found on the internet. Some of them are a bit old, some fairly new. They do a good job intruducing the software and the basic flow. Most of them are written for version 16.x but they can be used as introductions.

Forum Post: Active classes and sub-classes?

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I am somewhat new to making PCBs and components, I am using this video as a guild to learn how to make footprints "(Please visit the site to view this video) In the video, the first time she makes an assembly outline, she sets the class to Package geometry and the subclass to assembly_top, on the second chip however, when she draws the assembly outline, she uses the class of Board geometry and the subclass to silkscreen_top. I am not sure what the difference is, or which is even correct. Which class and subclass should be used to draw the assembly outline, silk screen, and package boundary? EDIT: link to video above https://www.youtube.com/watch?v=pKVn8_TKanM

Forum Post: RE: Closing the view file through SKILL

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Hi Andrew, Thanks for the quick help! It works. Regards, Jay

Forum Post: RE: viewing spectre simulation results right from the start

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You should also heed the advice given in the article that Quek refers to. Adjusting the minimum flush time is not too bad - it just allows quicker access to the results early in the simulation. However, there is a significant performance benefit that comes from writing the data in bigger chunks, and setting the maximum flush time rather defeats the benefit of that. I wouldn't anticipate that after a period of running a very long simulation it would be necessary to get updates more frequently than every 5 minutes. However, in the first few minutes I can see why you might want to ensure that something sensible is happening. Kind Regards, Andrew.

Forum Post: RE: Active classes and sub-classes?

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Apart from Areas, Keepins Keepouts and Boundaries, Classes and Subclasses in PCB Editor are used to control Visibility and Output and PCB Editor does not place any specific significance on what they are used for. By implication, the Package Geometry Class contains the Package Details and the Board Geometry Class contains the Board Details but this is not enforced by PCB Editor. For a Package, there can be Assembly details by layer, typically used for the output of Assembly drawings and there can be Silkscreen details, typically used for the output of the Silkscreen for manufacturing, and there can be numerous other, user defined, Subclasses. Assembly would typically go to Assembly Top (and / or Bottom), Silkscreen would typically go to Silkscreen Top (and / or Bottom) and the Package Boundary, being an area, would be required on Place Bound Top (and / or Place Bound Bottom)

Forum Post: RE: 17.2 alias key problems

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You need to get this issue reported to Cadence Support, either directly, or through your Cadence Channel Partner.
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