As I said earlier, this is supported in ADE XL. You can't use the start:step:stop syntax in the ADE L parametric set; that's why I said about ADE XL and ADE Assembler.
↧
Forum Post: RE: Sweeping 2 variables (at a time) in Parametric analysis
↧
Forum Post: RE: dump all the layer from Palette Assistant window in case of no LSW layer definitions in the specified technology database
leGetValidLayerList(techGetTechFile(geGetEditCellView()))
↧
↧
Forum Post: RE: Integrating Perl with Ocean
Are you manually modifying the input.scs in step 2? If so, when you run() the simulation in step 3, the input.scs will be recreated and it will lose the include line. You could add output_variables.txt to your modelFile() call, and then it would be included in the input.scs that OCEAN creates. Remember that OCEAN constructs the input.scs from the netlist you specify, plus the models, plus any design variables, plus any analysis statements, options, and signals to be saved. Regards, Andrew.
↧
Forum Post: RE: dump all the layer from Palette Assistant window in case of no LSW layer definitions in the specified technology database
works like charm!! Thank you so much Andrew. I can use this list to l_layers of hiCreateLayerCyclicField(). Before your idea, my thinking is to use all the layers and use a callback to check. But the challenge is how to write this callback? Thanks. Fred
↧
Forum Post: RE: dump all the layer from Palette Assistant window in case of no LSW layer definitions in the specified technology database
Fred, You could have used leIsLayerValid to check if each layer was a valid layer purpose pair - then you could use that to filter which of the complete LPP set was valid. Andrew
↧
↧
Forum Post: RE: dump all the layer from Palette Assistant window in case of no LSW layer definitions in the specified technology database
Andrew, Yes. That is what I am thinking. But the challenge is the mechanism of callback. The official doc has so limited info about callback. Thanks. Fred
↧
Forum Post: RE: dump all the layer from Palette Assistant window in case of no LSW layer definitions in the specified technology database
Fred, I don't think I really understand what you mean. It also depends which callback you're talking about - in what context? A callback is simply a function that gets called at a particular time - but unless I know what you're trying to do, I can't really give a more precise answer. Andrew.
↧
Forum Post: RE: dump all the layer from Palette Assistant window in case of no LSW layer definitions in the specified technology database
Andrew, There is "t_callback" from "hiCreateLayerCyclicField", but don't know how it works. Thanks. Fred
↧
Forum Post: layer map file for GDS transfer to virtuoso
Hello all, I have a GDS layout previously designed in SoC encounter, I want to import it in Virtuoso but I don't have a layer map provided with PDK (I'm using Nangate Open Cell Library 45nm). I now have two files; a technology file provided with PDK and a streamOut.map file generated from GDS export in Encounter. I need to understand the purpose of the map file and should I have provided it during GDS export in Encounter. If not, how to modify it for correct streamIn in Virtuoso. Here is part of the technology file: ; Technology File NCSU FreePDK 45nm ;******************************** ; LAYER DEFINITION ;******************************** layerDefinitions( techLayers( ;( LayerName Layer# Abbreviation ) ;( --------- ------ ------------ ) ( IP 63 IP ) ( nwell 3 nwell ) ( pwell 2 pwell ) ( nimplant 4 nimplant ) ( pimplant 5 pimplant ) ( active 1 active ) ( vtg 6 vtg ) ( vth 7 vth ) ( thkox 8 thkox ) ( poly 9 poly ) ( contact 10 contact ) ( metal1 11 metal1 ) ( via1 12 via1 ) ( metal2 13 metal2 ) ( via2 14 via2 ) ( metal3 15 metal3 ) ( via3 16 via3 ) ( metal4 17 metal4 ) ( via4 18 via4 ) ( metal5 19 metal5 ) ( via5 20 via5 ) ( metal6 21 metal6 ) ( via6 22 via6 ) ( metal7 23 metal7 ) ( via7 24 via7 ) ( metal8 25 metal8 ) ( via8 26 via8 ) ( metal9 27 metal9 ) ( via9 28 via9 ) ( metal10 29 metal10 ) ( DRC 400 DRC ) ) ;techLayers techLayerPurposePriorities( ;layers are ordered from lowest to highest priority ;( LayerName Purpose ) ;( --------- ------- ) ( IP drawing ) ( nwell drawing ) ( pwell drawing ) ( nimplant drawing ) ( pimplant drawing ) ( active drawing ) ( vtg drawing ) ( vth drawing ) ( thkox drawing ) ( poly drawing ) ( contact drawing ) ( metal1 drawing ) ( via1 drawing ) ( metal2 drawing ) ( via2 drawing ) ( metal3 drawing ) ( via3 drawing ) ( metal4 drawing ) ( via4 drawing ) ( metal5 drawing ) ( via5 drawing ) ( metal6 drawing ) ( via6 drawing ) ( metal7 drawing ) ( via7 drawing ) ( metal8 drawing ) ( via8 drawing ) ( metal9 drawing ) ( via9 drawing ) ( metal10 drawing ) ( DRC drawing ) ) ;techLayerPurposePriorities techDisplays( ;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid ) ;( --------- ------- ------ --- --- --------- ------- ----- ) ( IP drawing PacketName_0 t t t t t ) ( nwell drawing PacketName_2 t t t t t ) ------------------------------------------------------------------------------------------------------------------- and here is part of my streamOut.map file generated by Encounter: metal1 NET 1 0 metal1 SPNET 2 0 metal1 PIN 3 0 metal1 LEFPIN 4 0 metal1 FILL 5 0 metal1 FILLOPC 6 0 metal1 VIA 7 0 metal1 VIAFILL 8 0 metal1 VIAFILLOPC 9 0 metal1 LEFOBS 10 0 NAME metal1/NET 11 0 NAME metal1/SPNET 12 0 NAME metal1/PIN 13 0 NAME metal1/LEFPIN 14 0 via1 LEFPIN 15 0 via1 FILL 16 0 via1 FILLOPC 17 0 via1 VIA 18 0 via1 VIAFILL 19 0 via1 VIAFILLOPC 20 0 Any help would be appreciated
↧
↧
Forum Post: RE: layer map file for GDS transfer to virtuoso
If anyone can explain the purpose of map file and how to modify the map file, I'll be more than grateful. Thanks
↧
Forum Post: Compare Netlist Files
Hello, I have netlist file.I want to check which components have been added or removed from the previous version of netlist file. Orcad Capture or Allegro PCB Design Tool, which one need to use for this type of solution. ?
↧
Forum Post: RE: dump all the layer from Palette Assistant window in case of no LSW layer definitions in the specified technology database
Fred, The callbacks for all form fields are simply a SKILL expression that is evaluated whenever the form value changes (most of them when the focus moves away from that field). The idea is that the function you call then can react to the change the user has made to the field value, and either check the value they've specified (and do something with that) or compute the value of another field based on the current value of the field. So it would get called whenever you picked a different value for the layer-purpose in this field. I'm not sure it would be very useful to offer a complete list of layer-purposes in the choices, and then have the callback check to see if it's valid; it would probably be better just to provide the list of valid layer purposes as choices and then there's no need to check that in a callback. The use model would be a bit strange otherwise. Regards, Andrew
↧
Forum Post: RE: layer map file for GDS transfer to virtuoso
I took a look at the NCSU FreePDK45 (there's a link to download it from here after you've registered), and it doesn't contain a layer map file. From looking at the library, dumping the tech file, and comparing the layer numbers with those used in the various DRC and LVS rule files in the PDK, I can see that the OA/Virtuoso layer numbers correspond to the layer numbers in those rule files - so generally that means you wouldn't need a layer mapping file because the layer numbers for stream directly correspond to the OA/Virtuoso layer numbers. However, if you really needed one, you'd use: active drawing 1 0 pwell drawing 2 0 nwell drawing 3 0 nimplant drawing 4 0 pimplant drawing 5 0 vtg drawing 6 0 vth drawing 7 0 thkox drawing 8 0 poly drawing 9 0 contact drawing 10 0 metal1 drawing 11 0 via1 drawing 12 0 metal2 drawing 13 0 via2 drawing 14 0 metal3 drawing 15 0 via3 drawing 16 0 metal4 drawing 17 0 via4 drawing 18 0 metal5 drawing 19 0 via5 drawing 20 0 metal6 drawing 21 0 via6 drawing 22 0 metal7 drawing 23 0 via7 drawing 24 0 metal8 drawing 25 0 via8 drawing 26 0 metal9 drawing 27 0 via9 drawing 28 0 metal10 drawing 29 0 nodrc drawing 80 0 Note these numbers don't correspond to what you have in the stream map for Encounter. I'm not so familiar with Encounter, but a quick search on support.cadence.com gave me: Also this article: You may need to define a suitable layer map file for streaming out from encounter to match the stream layer numbers used in virtuoso and the physical verification tools; it looks as if the layer map file it generated was just an automatically generated file. You can probably adapt it to stream the data back into virtuoso, but it might be simpler to map it properly on the way out of Encounter. Overall though, this question would probably be best sent to NCSU - although it wasn't clear to me from the web sites how you contact them for assistance/guidance. Regards Andrew.
↧
↧
Forum Post: RE: layer map file for GDS transfer to virtuoso
Thank you Andrew, I will contact NCSU (eda_help@ncsu.edu **found in their PDK). Should I try attaching the map file you wrote during Encounter GDS export ?
↧
Forum Post: RE: layer map file for GDS transfer to virtuoso
[quote user="Omar Awad"]Should I try attaching the map file you wrote during Encounter GDS export ?[/quote] You might still need to adapt it so that the layer/purpose names match what is defined in the LEF (i.e. what they are called in Encounter). I suspect they're not called precisely the same thing... (I think metal1 NET rather than metal1 drawing). Andrew.
↧
Forum Post: Cadence Liberate: Path delays all zero in exported of verilog models
Hi there, I characterized custom cells for different corners and now want to create a verilog model for each corner. Although timings in the *.lib-file are totally different, path delay in all verilog models stay zero. Here are the steps I did to create the models: liberate > read_library lib/SUBVT28CORE_1.0_1.0_0_0_25_ecsm.lib Command line arguments: none. ALTOSHOME set to '/sct/homes3/cadence/liberate-15.14hf070'. Server ID : T20170228092209088037S0008335 liberate > read_library lib/SUBVT28CORE_1.0_1.0_0_0_25_ecsm.lib Reading 'lib/SUBVT28CORE_1.0_1.0_0_0_25_ecsm.lib' ... //LIBERATE parameter "enable_command_history" set to "0" LIBERATE parameter "slew_lower_rise" set to "0.3" LIBERATE parameter "slew_lower_fall" set to "0.3" LIBERATE parameter "slew_upper_rise" set to "0.7" LIBERATE parameter "slew_upper_fall" set to "0.7" LIBERATE parameter "measure_slew_lower_rise" set to "0.3" LIBERATE parameter "measure_slew_lower_fall" set to "0.3" LIBERATE parameter "measure_slew_upper_rise" set to "0.7" LIBERATE parameter "measure_slew_upper_fall" set to "0.7" LIBERATE parameter "delay_inp_rise" set to "0.5" LIBERATE parameter "delay_inp_fall" set to "0.5" LIBERATE parameter "delay_out_rise" set to "0.5" LIBERATE parameter "delay_out_fall" set to "0.5" Library read successfully. 1 liberate > write_verilog my.v Writing Verilog to my.v Writing Verilog for cell INV_X1 Looking at my.v gives: // type: `timescale 1ns/10ps `celldefine module INV_X1 (Z, A); output Z; input A; // Function not (Z, A); // Timing specify (A => Z) = 0; endspecify endmodule `endcelldefine Instead of the timing specification, I would expect something like this (example from 65nm lib): specify // delay parameters specparam tpllh$A$Z = 97:97:97, tphhl$A$Z = 74:74:74; // path delays (A *> Z) = (tpllh$A$Z, tphhl$A$Z); endspecify Why does liberate skip the timing annotation? Am I missing out some necessary configuration? Thanks in advance and best regards, Marten
↧
Forum Post: RE: Cadence Liberate: Path delays all zero in exported of verilog models
I suggest you contact customer support for this question. Regards, Andrew.
↧
↧
Forum Post: RE: layer map file for GDS transfer to virtuoso
In LEF file, metal1 type is "routing". I read this statement in Encounter User Guide : "Note: In routing layers, using ALL is the same as using NET, SPNET, VIA, PIN, LEFPIN, FILL, LEFOBS, and VIAFILL. In cut layers, using ALL is the same as using VIA or VIAFILL." So taking this part from streamOut.map file: ------------------- metal1 NET 1 0 metal1 SPNET 2 0 metal1 PIN 3 0 metal1 LEFPIN 4 0 metal1 FILL 5 0 metal1 FILLOPC 6 0 metal1 VIA 7 0 metal1 VIAFILL 8 0 metal1 VIAFILLOPC 9 0 metal1 LEFOBS 10 0 NAME metal1/NET 11 0 NAME metal1/SPNET 12 0 NAME metal1/PIN 13 0 NAME metal1/LEFPIN 14 0 via1 LEFPIN 15 0 via1 FILL 16 0 via1 FILLOPC 17 0 via1 VIA 18 0 via1 VIAFILL 19 0 via1 VIAFILLOPC 20 0 ---------------------------------------- I need to tell Encounter to map all metal1 layers to be "metal1 drawing 11 0", all NAME layers to be "metal1 label 11 0" and all via1 layers to be "via1 drawing 12 0" as required by Virtuoso. How can I do that using a layer map file that I'll attach it to Encounter GDS export ? --------------------------------------------------------- Also, what about this section: (it's not included in the automatically generated streamOut.map file by Encounter) active drawing 1 0 pwell drawing 2 0 nwell drawing 3 0 nimplant drawing 4 0 pimplant drawing 5 0 vtg drawing 6 0 vth drawing 7 0 thkox drawing 8 0 poly drawing 9 0 contact drawing 10 0 The only information related to this part in the LEF file is "LAYER poly TYPE MASTERSLICE ; END poly LAYER active TYPE MASTERSLICE ; END active"
↧
Forum Post: RE: layer map file for GDS transfer to virtuoso
As I've said before, Encounter (or Innovus) are not products that I generally cover, so I can't (personally) really answer the above. Potentially you'd be better off asking this in the Digital Implementation forum. My guess is that you alter all the metal1 entries to have "11 0" at the end, and so on. According tp the documentation you can reference the mapping file through the UI or using the -mapFile argument of the streamOut command. I wouldn't expect the stream file from Encounter to contain any of those layers (active, nwell, pwell etc) because these would be in the standard cells and not in the routing that Encounter is producing. Andrew.
↧
Forum Post: RE: Cadence Liberate: Path delays all zero in exported of verilog models
As a university customer support is not part of our contract... :-( Maybe you can give some hints? Should there be a delay writen in the verilog models or does timing get annoted after aplying a sdf file (post-synthesis)? Maybe SDF is sufficient then?!
↧