Are you part of the Europractice scheme? If so, you can get support via Europractice. If you're not part of Europractice, then usually support can be channelled via your contact point within your University. Some details can be found at: I don't spend that much time on Liberate myself, so I'd have to sit down and research this in more detail; because I answer questions in here in my spare time, and I really don't have any this week, I don't have the bandwidth to research and answer your question (if it had been something I could answer quickly, I would have done that already). Maybe somebody else will be able to, but we don't get a great number of Liberate questions on the forums... Regards, Andrew.
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Forum Post: RE: Cadence Liberate: Path delays all zero in exported of verilog models
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Forum Post: RE: layer map file for GDS transfer to virtuoso
Thanks Andrew ! Actually this was the point to attach the map file with correct layers in Encounter GDS export and I didn't need to attach the map file during streamIn in Virtuoso and everything worked perfectly. Thank you again!
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Forum Post: Generating a bit stream in Virtuoso
Hello all, I want to test a digital chip on Cadence Spectre using its extracted SPICE netlist from Calibre PEX. The chip has a bit stream of 128 bits as input and its outputs are: a digital bit stream of 128 bits and an analog signal. So what is the best way to generate the input bit stream ? I found a way using vbit source and loading a bit stream to it using a txt file, but is there a better way ?
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Forum Post: RE: Cadence Liberate: Path delays all zero in exported of verilog models
Hi Andrew, nevermind. Yeah I am wondering why so few questions about liberate are around here... I guess then I will have to contact europractice. Thank you very much for your effort.
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Forum Post: RE: Cadence Liberate: Path delays all zero in exported of verilog models
I'd have loved to have helped - just a bit constrained at the moment! The day job keeps getting in the way ;-)
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Forum Post: RE: Netlisting error - part references across multiple instances of hierarchical blocks
Thanks for the quick response, by the way - you didn't hear back because it worked!
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Forum Post: RE: Changing footprint text size in entire library
You can easily change the all the text in a board file or symbol at once. Not exactly what you're looking for but it is quick and it works. 1. Right Click > Super Fitler > Text 2. Edit > Change Objects 3. Check box for Text Block 4. Select Text Size. 5. Highlight all text. This will change all the text you highlight to the size that is selected.
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Forum Post: Create a DRC for Ref Des under part.
This there a way to create a DRC for Ref Des silkscreen inside a place_bound or DFA_bound shape? I'm tired of finding ref des hidden under a part after manufacturing.
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Forum Post: Donut Pad to Ground Connection
I am using the Pad Editor in Ver. 17.2-2016 S011 at the moment. I am trying to create a Pad Stack for a Non-Plated Mounting Hole that has a Donut Pad on the Outer Layers to connect to Ground. Chassis Ground are on Internal Layers so, within the Board, I will be placing a Via and then adding a Trace to the Copper Donut Pad. Once I define the Outer Layers as a Donut, the Usage Options at the bottom the Summary Page adds "Enable connect by touch: No" As I seem to need to use Touch, to connect it to a via, without a DRC violation, I am expecting that this should say "Yes". Richard
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Forum Post: Can't open cells in hierarchical schematic in Virtuoso
Hello all, I have a design in Cadence Virtuoso (originally designed in SoC Encounter using NangateOpenCellLibrary 45nm std cells), when I try to open any std cell in the design schematic, I get these warnings and the std cell schematic open having all pins (inputs and outputs) marked as "unbound" *WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist. *WARNING* (DB-270337): Failed to open cellView (opin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist. *WARNING* Missing Masters: Library Cell View NangateOpenCellLibrary ipin symbol NangateOpenCellLibrary opin symbol and when I try to run LVS (between imported GDS layout and verilog netlist exported from Encounter), I get a bunch of these errors: ERROR (OSSHNL-366): Instance 'I4' in cellview 'NangteOpenCellLibrary/AND2_X4/schematic' is bound to placed master 'NangateOpenCellLibrary/ipin/symbol'. However, OSS has determined that it is not a valid placed master. Ensure that cds.lib has entries for all the reference libraries and netlist again. Correct this error and netlist again. *WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist. *WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist. *WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist. *WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist. Any suggestions ?
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Forum Post: RE: Can't open cells in hierarical schematic in Virtuoso
Where did you get the library from? I just downloaded the NangateOpenCellLibrary_PDKv1_3_v2010_12.tgz version from: which I got to from a bit of a google search - from In this kit, I looked in NangateOpenCellLibrary_PDKv1_3_v2010_12/Back_End/virtuoso and there's a library NangateOpenCellLibrary; if I open AND2_X4/schematic from this library, the pins are found OK - they are contained within that library (you can see them in the library manager). So I can only assume you've got the library from somewhere else, it's a different version, or somebody has messed with it. Regards, Andrew.
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Forum Post: RE: Generating a bit stream in Virtuoso
By "128 bits" do you mean it's 128 bits wide? If so, you are probably going to be better creating a vector file - this is available via the Setup->Simulation Files form in ADE and is documented in a chapter in the Ultrasim User Guide (on "Digital Vector File Format"). See this recent thread on vector files (just FYI - it gives some examples, at least). Regards, Andrew.
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Forum Post: RE: Create a DRC for Ref Des under part.
Search this forum for AutosilkUtils. Let me know if you have any questions.
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Forum Post: RE: mixed-signal AMS simulation error
how did you resolve this in the end ? I'm getting the same error...
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Forum Post: RE: A few questions regarding using PSS for rectifier design
Hi Andrew, Thank you very much for your help regarding the setting of reltol in the ADE, and the results did improve after setting reltol=1e-6 I'm a PhD student, to contact the customer support, I have to go through a lengthy process with the university... Also, do you think tightening max_time_step will help further improve the simulation accuracy (for both transient and harmonic balance)? Regards, Menghan
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Forum Post: RE: Tcl script, for library manipulation
Thanks, Using this CapLibpropUtil.tcl we can add property value to all library symbols( only same value). If i want to process each symbol seperately, is there any command to get each symbol and add corresponding value to property. oldmouldy, thanks in advance :)
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Forum Post: RE: mixed-signal AMS simulation error
Clearly the simplest way to solve it is to use a newer version of INCISIVE. Which version are you using? Andrew.
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Forum Post: RE: A few questions regarding using PSS for rectifier design
Generally messing with maxstep is unnecessary (it won't help harmonic balance anyway), and the better solution is to ask for more harmonics in shooting PSS (this affects maxacfreq, which in turn affects maxstep during the shooting interval)). I'm not sure why you refer to max_time_step as there's no such parameter in spectre. However, without knowing more detail, I don't like giving advice about changing a parameter without understanding the root cause of the accuracy issues. Andrew
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Forum Post: import physical verilog netlist in Virtuoso
I generated a physical verliog netlist for my design in Encounter using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst". Here is the explanation of every attribute in this command: -phys: Writes out physical cell instances, and inserts power and ground nets in the netlist. This is used for LVS and for designs with multiple supply voltages. -includePowerGround: Includes power and ground connections in the netlist file. -includePhysicalInst: Includes physical instances, such as fillers. WhenI try to import this netlist in Virtuoso, I get these warnings for all std cells: WARNING (VERILOGIN-111): Cannot connect the terminal VDD in symbol AOI211_X1 as it does not have a pin. WARNING (VERILOGIN-111): Cannot connect the terminal VSS in symbol AOI211_X1 as it does not have a pin. WARNING (VERILOGIN-551): Number of pins on symbol DFF_X2 in library NangateOpenCellLibrary differ from the number of ports in the HDL module description. When I open the symbol of DFF_X2, there is no VDD and VSS symbol, so should I update the symbol of all std cells manually to have the VDD and VSS symbols ? (I can find "VDD!" and "VSS!" pins in DFF_X2 schematic but not in its symbol) Additionally, I get these warnings for FILLER cells: WARNING (VERILOGIN-72): Could not find the symbol master for the instance FILLER_5. Therefore the functional view will not have this instance. And again there is no symbol view for FILLER cells in the std cell library. Since, all std cells schematics have VDD! and VSS! pins but their symbols don't, was this made so that Virtuoso power these pins virtually without an explicit power source and ground ? or this is wrong and I have to update all symbols manually ? Finally, power and ground are called "VDD" and "VSS" respectively in my verilog netlist, however they are written as "VDD!" and "VSS!" in all std cells schematics. So what is the difference between "VDD" and "VDD!" ? Thanks
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Forum Post: RE: dump all the layer from Palette Assistant window in case of no LSW layer definitions in the specified technology database
Andrew, Totally agree what you said. The callback way works. If a user selects a LPP, the callback will check(form->layerField->value ---> techGetLP ---> techGetLPAttr) if it is valid in technology database. If it is invalid, it just tell the user and quit. But that is not good solution. The good solution is like what you elaborated here, just give all the valid LPPs to user. Thanks. Fred
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