Hi everybaby, I am getting extrange behabiour in assura. I have 2 digital blocks A and B sintetized independently and we have added prefixes A_... B_... to the corresponding subcircuits in to avoid problems when put together. When placed together, they have independent power rails. The LVS are clean if run independently but when they are put together i get a lot of parameter mismatch in cells made up by feedthrough cells from the std. library of the technology. Suppose i have the cells feed1, feed2...feedn from the standard lib. When I open the LVS Debug Env. and i open the mismatches it shows that what is in the schematic feed2 is in the layout feed7 (for example). Like this many other similar. I found out the ambiguities message during the LVS run as weel. For me looks like assura is mixing the feedthrough cells. Since the feed cells in a block are all connected to the same VDD and GND the circuits match (instances, nets...) but the parameters not. The autoswappin option is "off". I hope somebody can elucidate some solution the problem or hint. Best regards, Manuel
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Forum Post: Assura problems with feedthrough caps
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Forum Post: Spectre: use models on a per module basis?
Hello! Is it possible to tell Spectre to use different models for the same devices in different modules? Our design kit has standard and "PRE_SIMU" models (=include contact-to-poly caps and parasitic contact and gate resistances) for the MOS devices, and we would like to use these PRE_SIMU models only for the devices in specific modules, at different moments in the design cycle: -In the early design phases, use PRE_SIMU models only for the critical blocks in the system, and standard for the rest (speeds up simulation time) -In the later design phases, use PEX views for the already laid-out critical blocks, and PRE_SIMU models for everything else not yet laid-out. Currently all I can do is define these models globally for all the devices using the Model Library Setup window (need just to include a section from the model libraries). However, as soon as I use PEX views, I need to switch back to the standard models, as using PRE_SIMU globally would yield incorrect results due to double-counting of parasitics in the modules with PEX views. Thus the accuracy of our simulations gets compromised as we proceed into the implementation cycle and start to add PEX views. ...any ideas on how to overcome this problem? Thanks in advance for any help. Jorge.
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Forum Post: Adding Layers to a micro via design
Is there any information on what happens to the micro-vias when you add layers to the design.
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Forum Post: SKILL descend into a component sub-circuit schematic
Dear all, I'm currently working on a impedance matching tool that will be run using Cadence SKILL and OCEAN and have stumbled upon a small problem. I'd like to do the following: 1) Open an existing schematic that has components inside. Each of the components have sub-circuits inside, but they are not parametric cells. 2) Descend into a particular component and change the value of a component which is inside the sub-circuit parameter. In other words I have a top level schematic A that has a component B. And I want to access component C parameters which is a sub-circuit inside of a component B in the top level schematic A. I know how to open a schematic, find and change the parameters of an existing component (in this case it is component "Cpad1" in a schematic "ind_lossy" in a library LIB_NAME): cvIdTemp = dbOpenCellViewByType(LIB_NAME "ind_lossy" "schematic") dbReopen(cvIdTemp "a") ;to remove locked status of the opened cell view instanceSelection= dbFindAnyInstByName(cvIdTemp "Cpad1") instanceSelection ~>c = 123e-12 dbSave(cvIdTemp) dbClose(cvIdTemp) I was wondering - how would one descend into a component sub-circuit schematic and change parameters inside using SKILL, save and close both the sub-circuit and the top schematic? Thanks, Aleksandr
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Forum Post: RE: Spectre: use models on a per module basis?
Hi Jorge, ADE XL (and ADE Explorer/Assembler in IC617) has a capability called "MTS" (Multi Technology Simulation) which enables this. You have to do the following: You must have a config for the design and have it as the config that you're simulating in a test Over the test name in ADE XL/Explorer/Assembler use Right Mouse->Simulator, or in the test editor use Setup->Simulator and enable the Multi-Technology Mode checkbox Then using Right Mouse->MTS Options over the test (it's near the bottom of the menu) you can enable different model files for different cells, or for different instances. You can also control a few other parameters (such as the temperature, scale factors and so on). This then produces a scoped netlist for spectre where the models are included at the appropriate points in the design hierarchy; you can have the same model names used in different parts of the design hierarchy. Theoretically this was an ADE GXL feature, but since IC616 (at least) it's been available in ADE XL without needing a GXL license. Regards, Andrew.
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Forum Post: RE: mixed-signal AMS simulation error
INCISIV11. so, it's purely tool version issue ? I'll ask IT to upgrade it. Thanks a lot !
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Forum Post: RE: import physical verilog netlist in Virtuoso
OK, first thing to consider is whether you actually have multiple powers and grounds. This symbol library (from the look I've had at it) isn't designed to support multiple powers and grounds; each schematic has a global power and ground called VDD! and VSS! (in Virtuoso, global signals are typically suffixed with an exclamation mark). That means that all the powers and grounds in the standard cells themselves do not have distinct connections. There are pins (with global names) on the schematic, but not on the symbols. If you don't have multiple powers and grounds on the physical implementation side, don't use the -includePowerGround. Maybe you don't need -phys wither. If you don't have symbols for the filler cells, I suggest you omit the -includePhysicalInst. If you do have multiple powers and grounds in the design, the best way to achieve this is to edit the schematics for the standard cells. You'll need to do this for all of them (bear in mind they weren't designed for this use model, so it's a bit of work - although not too painful). Edit the VDD! pin and change the name to VDD. You'll find probably there's a small (blue) text label next to the pin that also renames from VDD! to VDD. Remove this label. Do the same for VSS! - change that to VSS and remove the VSS label. Use Create->Net Expression and fill in the property as VDD and default value as VDD!. Then click on the VDD pin Do the same for the VSS pin (property VSS, default value VSS! and click on the VSS pin) Check and save the schematic Now, when you do an Import Verilog (I don't know which version you're using - this is for IC617), go to the Schematic Generation Options tab and expand the "Reference Schematic View for Inherited Connections". In the List of Views field that appears, enter "schematic". In IC616 it's on the same tab, but is called Reference Schematic Views and is about three-quarters of the way down the form. Then what will happen is that when you import the Verilog, it will see that the instance in the Verilog has VDD and VSS pins, and it will then look for these pins in the reference schematic view and instead of connecting up a pin, it will add a netSet property on the instance to connect the power connections using inherited connections. Regards, Andrew.
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Forum Post: RE: mixed-signal AMS simulation error
Well, I'm not sure why ADE thinks you are using a simulator that has the feature (it shouldn't), but the simplest way to fix it would be to use something more recent (especially as INCISIV11 is 5-6 years old). Andrew
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Forum Post: Allegro Design Entry, Text input window bug
When you place a text on a schematic there is a window to edit its pro perties, and that window is cropped and not adjustable. Please fix this ASAP!
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Forum Post: RE: Spectre: use models on a per module basis?
Thanks so much for your prompt reply, Andrew; I just tried it and it solves our main problem! Thanks so much! I noticed however that it's not possible to define models on a per-instance basis (when I switch to the "Instance tree" view, the "modelFiles" field isn't available anymore).... can you please confirm if this is the case? Cheers, Jorge.
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Forum Post: RE: import physical verilog netlist in Virtuoso
Hello Andrew, Thank you for your reply. I can't find any VDD or VSS in the exported verliog netlist without any attributes ("saveNetlist design.v"), so I don't know if this will be ok in verilog import in Virtuoso. I'm using IC614 (sorry for being outdated). Here is my .ihdlParamFile: DirLabel =/root/Desktop/AES128bits/encounter Target Library = NangateOpenCellLibrary Reference Libraries =NangateOpenCellLibrary Verilog Design Files = design.v -y Options = Library Extn. = -v Options = -f Options = Ignore Modules File = Import Modules File = Log File =./verilogIn.log Work Area =/tmp Power Net =VDD! Ground Net =VSS! Global Signals = Net Expression Property Name for Power Net =vdd Net Expression Property Name for Ground Net =gnd Create Net Expression =false Connect By Name Nets = Import Modules That Match Existing Target Library Cells =false Verilog Cell Modules =Create Symbol Only Verilog Structural Modules View =schematic Functional View Name =functional Netlist View Name =netlist Schematic View Name =schematic Symbol View Name =symbol Name Map Table = ./verilogIn.map.table Sheet Size =none Pin Placement Flag =Left and Right Sides Pin Placement File = Label Size =0.062500 Maximum Number Of Rows =1024 Maximum Number of Columns =1024 Line-Line Spacing = 0.20000 Line-Component Spacing = 0.50000 Density Level =0 Full Place and Route =true Fast labels =false Minimize Cross Over =false Generate Square Schematics =true Extract Schematics =true Ignore Extra Pins =false No Dummy Nets In Netlist View =false Verbose =false Generate Snap Space Properties =true Through CellView Library =basic Through CellView Cell =cds_thru Through CellView View =symbol Continuous Assignment CellView Library =basic Continuous Assignment CellView Cell =patch Continuous Assignment CellView View =symbol Pre Compiled Library = Destination IR Lib = ViewName for IR Library =hdl Only Compile a Verilog Library =false Can you tell me what to change ?
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Forum Post: RE: Donut Pad to Ground Connection
In order to make the mounting hole able to connect to a net you will need to create a part (.dra) and add the pad as a pin. You can then create a part in capture and make the necessary connections.
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Forum Post: RE: Donut Pad to Ground Connection
I did make a "Mechanical" Part and added the Pad Stack as a pin. I then placed the Part manually onto the board. Then I tried to connect a via to it. Visually it looks fine, but the DRC Marks it as an error. I did try and add it, as you mention, as an "Electrical" part, and, added within Capture with a connection to Ground, but, by doing it that way, the Inner Layer Planes would connect also. As it is a non-plated hole, even without inner layer pads, it would create thermal ties to the hole.
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Forum Post: RE: Spectre: use models on a per module basis?
Hi Jorge, Sorry - I was mistaken (I'd forgotten) - you can't specify model files on a per-instance basis; only on a per-cell basis. That's expected. Regards, Andrew.
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Forum Post: RE: import physical verilog netlist in Virtuoso
Do you need to change anything? There's generally no need to have power in the verilog if there's only one set of supplies. The supply connections are defined as globals within the standard cells; there's no need for them to be mentioned in the Verilog in that case (in general digital designers are concerned about the signal flow, not the supplies). The symbols don't have supplies on them in the library, so nothing needs to be connected up. It's unclear to me if anything isn't working for you if you import the Verilog which doesn't contain power/ground information. I'd expect that to work... if it doesn't, you'd need to explain what doesn't work. Andrew.
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Forum Post: RE: Allegro Design Entry, Text input window bug
This is a community user forum not the Cadence support login. For enhancement requests, log in to your support account and request this upgrade. Oh, and good luck.
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Forum Post: Align pins based on connectivity
Hi, I'm looking for a function which can align pins to objects with similar net name. For example say I have an instance and pins only in layout. Now I want to place pins directly over the instance's pins. In Edit->Advanced->Align there is an option to do this but I get the following error. *WARNING* (LX-3009): Cannot run pin alignment because there are no pin pairs to be aligned. Can somebody help me? I'm using virtuoso version ICADV12.2-64b 04/13/2016 08:41 -Ramakrishnan
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Forum Post: RE: Spectre: use models on a per module basis?
OK, good to know. Thanks so much again, Andrew! Cheers, Jorge.
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Forum Post: RE: Assura problems with feedthrough caps
Manuel, Debugging this in a forum without being able to see the data would be very hard. Please can you contact customer support for this. Regards, Andrew.
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Forum Post: RE: Cadence Liberate: Path delays all zero in exported of verilog models
Nevermind Andrew, I only know a few ambitious forum moderators and one of them is you ;-) Besides, I could solve the problem: write_verilog -specparams -table-style min-avg-max my.v enables the desired behaviour. Neverthless, these results in optimistic/pessimistic timing models, so anotating an SDF is preferable for more accurate timing simulations.
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